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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:47:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:47:39 +0100 |
| commit | 1f1deda888ea32ade2478fca9fcb510ada477606 (patch) | |
| tree | bf21e5e60e970745af2d4652addfbe383f6b4187 /frontends/verilog/verilog_lexer.l | |
| parent | b005eedf369bc60ce5f7cba9a0db4694f22a360f (diff) | |
| download | yosys-1f1deda888ea32ade2478fca9fcb510ada477606.tar.gz yosys-1f1deda888ea32ade2478fca9fcb510ada477606.tar.bz2 yosys-1f1deda888ea32ade2478fca9fcb510ada477606.zip | |
Added non-std verilog assume() statement
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 13b3e2bfc..3a57514aa 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -166,8 +166,9 @@ YOSYS_NAMESPACE_END "always_ff" { SV_KEYWORD(TOK_ALWAYS); } "always_latch" { SV_KEYWORD(TOK_ALWAYS); } -"assert" { SV_KEYWORD(TOK_ASSERT); } -"property" { SV_KEYWORD(TOK_PROPERTY); } +"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); } +"assume" { if (formal_mode) return TOK_ASSUME; return TOK_ID; } +"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); } "logic" { SV_KEYWORD(TOK_REG); } "bit" { SV_KEYWORD(TOK_REG); } |