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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-26 01:52:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-26 01:52:59 +0200 |
| commit | 2cc09161ffd774430293dfd18e307e75bea73c5e (patch) | |
| tree | 9c018ea7954daddaaa8e6cc89502ed522f3a30a9 /frontends/verilog/verilog_lexer.l | |
| parent | 143c0abd33ed76b2a7e38dbbac1767e6f7edd68f (diff) | |
| download | yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.tar.gz yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.tar.bz2 yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.zip | |
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 885332b76..07d85bed8 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -389,10 +389,6 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { \\[\r\n] /* ignore continuation sequence */ "//"[^\r\n]* /* ignore one-line comments */ -"#"\ *[0-9][0-9_]* /* ignore simulation timings */ -"#"\ *[0-9][0-9_]*\.[0-9][0-9_]* /* ignore simulation timings */ -"#"\ *[$a-zA-Z_\.][$a-zA-Z_0-9\.]* /* ignore simulation timings */ - . { return *yytext; } %% |