diff options
| author | Udi Finkelstein <github@udifink.com> | 2018-03-04 23:35:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-27 14:34:00 +0200 |
| commit | 6378e2cd46711fed551ecf3201cee1f174d7053d (patch) | |
| tree | 2560746b61bd2da76e8add38ca57adc30d086a09 /frontends/verilog/verilog_lexer.l | |
| parent | f3eaa0ffa54ddaea4bf4e04acc1b2e019e22484a (diff) | |
| download | yosys-6378e2cd46711fed551ecf3201cee1f174d7053d.tar.gz yosys-6378e2cd46711fed551ecf3201cee1f174d7053d.tar.bz2 yosys-6378e2cd46711fed551ecf3201cee1f174d7053d.zip | |
First draft of Verilog parser support for specify blocks and parameters.
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index d6d00c371..32d7738cf 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -145,6 +145,9 @@ YOSYS_NAMESPACE_END "endfunction" { return TOK_ENDFUNCTION; } "task" { return TOK_TASK; } "endtask" { return TOK_ENDTASK; } +"specify" { return TOK_SPECIFY; } +"endspecify" { return TOK_ENDSPECIFY; } +"specparam" { return TOK_SPECPARAM; } "package" { SV_KEYWORD(TOK_PACKAGE); } "endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); } "parameter" { return TOK_PARAMETER; } |