| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 3 | -99/+69 |
| * | Make and dependent upon LSB only | ZipCPU | 2018-11-03 | 1 | -2/+8 |
| * | Do not generate "reg assigned in a continuous assignment" warnings for "rand ... | Clifford Wolf | 2018-11-01 | 1 | -2/+15 |
| * | Improve read_verilog range out of bounds warning | Clifford Wolf | 2018-10-20 | 1 | -6/+6 |
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 3 | -134/+108 |
| * | Support for SystemVerilog interfaces as a port in the top level module + test... | Ruben Undheim | 2018-10-20 | 1 | -3/+105 |
| * | Fixed memory leak | Ruben Undheim | 2018-10-20 | 1 | -0/+1 |
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 4 | -14/+265 |
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| | * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 2 | -8/+35 |
| | * | Fix build error with clang | Ruben Undheim | 2018-10-12 | 1 | -1/+1 |
| | * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 3 | -5/+68 |
| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 4 | -14/+175 |
| * | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 |
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| | * | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 |
| | * | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 4 | -237/+254 |
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| | * | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 |
| * | | | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 |
| * | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 |
| * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
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| * | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 2 | -8/+11 |
| * | | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 1 | -4/+4 |
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| | * | | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -4/+4 |
| * | | | Merge pull request #590 from hzeller/remaining-file-error | Clifford Wolf | 2018-08-15 | 1 | -15/+15 |
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| | * | | | Fix remaining log_file_error(); emit dependent file references in new line. | Henner Zeller | 2018-07-20 | 1 | -15/+15 |
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| * | | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 3 | -2/+50 |
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| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 3 | -7/+40 |
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 3 | -2/+17 |
| * | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 3 | -132/+128 |
| * | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 2 | -77/+76 |
| * | | Provide source-location logging. | Henner Zeller | 2018-07-19 | 1 | -3/+2 |
| * | | Fix handling of signed memories | Clifford Wolf | 2018-06-28 | 1 | -0/+3 |
| * | | Add (* gclk *) attribute support | Clifford Wolf | 2018-06-01 | 1 | -0/+9 |
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 2 | -6/+14 |
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| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 2 | -3/+3 |
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -0/+1 |
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 2 | -2/+2 |
| * | Fix error handling for nested always/initial | Clifford Wolf | 2017-12-02 | 2 | -0/+5 |
| * | Remove some dead code | Clifford Wolf | 2017-10-10 | 1 | -15/+0 |
| * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 |
| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 2 | -14/+14 |
| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 1 | -1/+1 |
| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -17/+17 |
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -10/+40 |
| * | enable $bits() and $size() functions only when the SystemVerilog flag is enab... | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 |
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -2/+26 |
| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -1/+3 |
| * | Add $size() function. At the moment it works only on expressions, not on memo... | Udi Finkelstein | 2017-09-26 | 1 | -0/+14 |
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons... | Clifford Wolf | 2017-06-07 | 1 | -0/+7 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 4 | -3/+12 |
| * | Preserve string parameters | Clifford Wolf | 2017-02-23 | 1 | -2/+8 |
