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| author | Henner Zeller <h.zeller@acm.org> | 2018-07-19 09:40:20 -0700 | 
|---|---|---|
| committer | Henner Zeller <h.zeller@acm.org> | 2018-07-19 10:22:02 -0700 | 
| commit | 1a60126a3468c525ac31de930dfb139b70512a34 (patch) | |
| tree | 37a93a112c809c11cdecae91ed7042bea0dd793f /frontends/ast | |
| parent | 87aef8f0cc9ee63fc8fe5eb26e6ceb73aa83b5c9 (diff) | |
| download | yosys-1a60126a3468c525ac31de930dfb139b70512a34.tar.gz yosys-1a60126a3468c525ac31de930dfb139b70512a34.tar.bz2 yosys-1a60126a3468c525ac31de930dfb139b70512a34.zip  | |
Provide source-location logging.
o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 5 | 
1 files changed, 2 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d9f0039af..b8208fa80 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -958,9 +958,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)  				wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);  				wire->name = str;  				if (flag_autowire) -					log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); +					log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());  				else -					log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum); +					log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());  			}  			else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {  				if (id2ast->children[0]->type != AST_CONSTANT) @@ -1563,4 +1563,3 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL  }  YOSYS_NAMESPACE_END -  | 
