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| author | Udi Finkelstein <github@udifink.com> | 2017-09-26 09:19:56 +0300 |
|---|---|---|
| committer | Udi Finkelstein <github@udifink.com> | 2017-09-26 09:19:56 +0300 |
| commit | 7e391ba90438ba1c20c29863d1556cb6bfd1ea29 (patch) | |
| tree | e56bd5bccb49cbb126f8f5a57270ea74a9d7b0a3 /frontends/ast | |
| parent | 2dea42e9039cdf47ca4927f62c69c6ae7ac2e399 (diff) | |
| download | yosys-7e391ba90438ba1c20c29863d1556cb6bfd1ea29.tar.gz yosys-7e391ba90438ba1c20c29863d1556cb6bfd1ea29.tar.bz2 yosys-7e391ba90438ba1c20c29863d1556cb6bfd1ea29.zip | |
enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/simplify.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 0cde34dc5..5b7e48361 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1870,7 +1870,7 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } - if (str == "\\$size" || str == "\\$bits") + if (VERILOG_FRONTEND::sv_mode && (str == "\\$size" || str == "\\$bits")) { if (children.size() != 1) log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", |