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| author | Clifford Wolf <clifford@clifford.at> | 2018-01-05 13:28:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-01-05 13:28:45 +0100 |
| commit | c80315cea42414216bcc7b62acb2ef9a41b54eab (patch) | |
| tree | bc089997bff5a8d906fc652441fdff803add06dd /frontends/ast | |
| parent | fefb652d568749731b581185e6cb201f0fff479e (diff) | |
| download | yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.tar.gz yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.tar.bz2 yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.zip | |
Bugfix in hierarchy handling of blackbox module ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 2 | ||||
| -rw-r--r-- | frontends/ast/ast.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index be04d5536..037a9f3ee 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1067,7 +1067,7 @@ AstModule::~AstModule() } // create a new parametric module (when needed) and return the name of the generated module -RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters) +RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool) { std::string stripped_name = name.str(); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index a5d5ee30a..d1e2c78d1 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -283,7 +283,7 @@ namespace AST AstNode *ast; bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; virtual ~AstModule(); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail); virtual RTLIL::Module *clone() const; }; |