diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-05-03 15:25:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-03 15:25:59 +0200 |
| commit | a572b495387743a58111e7264917a497faa17ebf (patch) | |
| tree | 103a3523b1868e31ec88d9b56ceb750f824bf487 /frontends/ast | |
| parent | e060375f23d56b4e330a946d5a626f0163499618 (diff) | |
| download | yosys-a572b495387743a58111e7264917a497faa17ebf.tar.gz yosys-a572b495387743a58111e7264917a497faa17ebf.tar.bz2 yosys-a572b495387743a58111e7264917a497faa17ebf.zip | |
Replace -ignore_redef with -[no]overwrite
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 18 | ||||
| -rw-r--r-- | frontends/ast/ast.h | 2 |
2 files changed, 14 insertions, 6 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 037a9f3ee..999202b47 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1003,7 +1003,7 @@ static AstModule* process_module(AstNode *ast, bool defer) // create AstModule instances for all modules in the AST tree and add them to 'design' void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, - bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire) + bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) { current_ast = ast; flag_dump_ast1 = dump_ast1; @@ -1042,12 +1042,20 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump (*it)->str = "$abstract" + (*it)->str; if (design->has((*it)->str)) { - if (!ignore_redef) + RTLIL::Module *existing_mod = design->module((*it)->str); + if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { log_error("Re-definition of module `%s' at %s:%d!\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); - log("Ignoring re-definition of module `%s' at %s:%d!\n", - (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); - continue; + } else if (nooverwrite) { + log("Ignoring re-definition of module `%s' at %s:%d.\n", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + continue; + } else { + log("Replacing existing%s module `%s' at %s:%d.\n", + existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + design->remove(existing_mod); + } } design->add(process_module(*it, defer)); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d1e2c78d1..756629aca 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -275,7 +275,7 @@ namespace AST // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, - bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); + bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions |