| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 4 | -9/+118 |
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| | * | frontends/ast: code style | David Shah | 2019-10-03 | 1 | -2/+1 |
| | * | sv: Fix typedefs in blocks | David Shah | 2019-10-03 | 1 | -2/+2 |
| | * | sv: Add support for memories of a typedef | David Shah | 2019-10-03 | 1 | -6/+20 |
| | * | sv: Add support for memory typedefs | David Shah | 2019-10-03 | 1 | -2/+15 |
| | * | sv: Fix typedefs in packages | David Shah | 2019-10-03 | 1 | -4/+10 |
| | * | sv: Fix typedef parameters | David Shah | 2019-10-03 | 1 | -2/+31 |
| | * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 4 | -7/+55 |
| * | | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 |
| * | | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 |
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| * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #... | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
| * | Fix handling of range selects on loop variables, fixes #1372 | Clifford Wolf | 2019-09-16 | 1 | -2/+9 |
| * | Merge pull request #1350 from YosysHQ/clifford/fixsby59 | Clifford Wolf | 2019-09-05 | 1 | -7/+18 |
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| | * | Properly construct $live and $fair cells from "if (...) assume/assert (s_even... | Clifford Wolf | 2019-09-02 | 1 | -7/+18 |
| * | | Remove newline | Eddie Hung | 2019-08-29 | 1 | -1/+0 |
| * | | Restore non-deferred code, deferred case to ignore non constant attr | Eddie Hung | 2019-08-29 | 1 | -5/+12 |
| * | | read_verilog -defer should still populate module attributes | Eddie Hung | 2019-08-28 | 1 | -5/+6 |
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| * | Do not propagate mem2reg attribute through to result | Eddie Hung | 2019-08-22 | 1 | -1/+2 |
| * | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 1 | -0/+4 |
| * | handle real values when deriving ast modules | Jakob Wenzel | 2019-08-19 | 1 | -1/+4 |
| * | Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad... | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
| * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 1 | -1/+1 |
| * | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 3 | -14/+14 |
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| | * | substr() -> compare() | Eddie Hung | 2019-08-07 | 3 | -6/+6 |
| | * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -7/+7 |
| | * | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 1 | -15/+2 |
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| | * | | IdString::str().substr() -> IdString::substr() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
| * | | | Allow whitebox modules to be overwritten | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
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| * | | Fix handling of functions/tasks without top-level begin-end block, fixes #1231 | Clifford Wolf | 2019-08-06 | 1 | -15/+2 |
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| * | initialize noblackbox and nowb in AstModule::clone | Jakob Wenzel | 2019-07-22 | 1 | -0/+2 |
| * | genrtlil: emit \src attribute on CaseRule. | whitequark | 2019-07-08 | 1 | -0/+1 |
| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 3 | -6/+29 |
| * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 3 | -46/+34 |
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 4 | -4/+49 |
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| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 4 | -4/+49 |
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 3 | -5/+28 |
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| | * \ | Merge pull request #1044 from mmicko/invalid_width_range | Clifford Wolf | 2019-05-27 | 1 | -1/+2 |
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| | | * | | Give error instead of asserting for invalid range, fixes #947 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+2 |
| | * | | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 3 | -4/+26 |
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| * | | | remove leftovers from ast data structures | Stefan Biereigel | 2019-05-27 | 2 | -4/+0 |
| * | | | move wand/wor resolution into hierarchy pass | Stefan Biereigel | 2019-05-27 | 1 | -97/+14 |
| * | | | fix assignment of non-wires | Stefan Biereigel | 2019-05-23 | 1 | -16/+19 |
| * | | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 3 | -61/+81 |
| * | | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 3 | -14/+83 |
| * | | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 1 | -1/+1 |
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| * | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -1/+30 |
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| | * | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -0/+3 |
| | * | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 2 | -0/+12 |
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| | * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 2 | -2/+8 |
| | * | | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 |
