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| author | David Shah <davey1576@gmail.com> | 2019-08-10 17:14:48 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-10 17:14:48 +0100 |
| commit | f9020ce2b35f2fc205fc71cb095efce1a24fd86d (patch) | |
| tree | 73ac462dd723cc389070cea893ddc9c1998339a2 /frontends/ast | |
| parent | f54bf1631ff37a83733c162e6ebd188c1d5ea18f (diff) | |
| download | yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.gz yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.tar.bz2 yosys-f9020ce2b35f2fc205fc71cb095efce1a24fd86d.zip | |
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 0d6626b19..07ef0a86e 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); - if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { + if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str()); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s:%d.\n", |