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| author | Jakob Wenzel <wenzel@rs.tu-darmstadt.de> | 2019-08-19 14:17:36 +0200 |
|---|---|---|
| committer | Jakob Wenzel <wenzel@rs.tu-darmstadt.de> | 2019-08-19 14:17:36 +0200 |
| commit | 24971fda87e66af528aeeffab841a64fc960410a (patch) | |
| tree | f7d6e4bdfa65c7ad6f3ffd15b91a8807dd347b11 /frontends/ast | |
| parent | 4adcbecec5c6bfcdd3ed1d6ed753d3a7670e3eea (diff) | |
| download | yosys-24971fda87e66af528aeeffab841a64fc960410a.tar.gz yosys-24971fda87e66af528aeeffab841a64fc960410a.tar.bz2 yosys-24971fda87e66af528aeeffab841a64fc960410a.zip | |
handle real values when deriving ast modules
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 0d6626b19..82283fb5b 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1502,7 +1502,10 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString rewrite_parameter: para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); delete child->children.at(0); - if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0) + if ((parameters[para_id].flags & RTLIL::CONST_FLAG_REAL) != 0) { + child->children[0] = new AstNode(AST_REALVALUE); + child->children[0]->realvalue = std::stod(parameters[para_id].decode_string()); + } else if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0) child->children[0] = AstNode::mkconst_str(parameters[para_id].decode_string()); else child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0); |