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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:40:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:40:24 -0700 |
| commit | 9776084eda50060594c6609295c7aa540bb400e1 (patch) | |
| tree | 5e2b503ebc6e5f12048be338e69ee2c0c8a81880 /frontends/ast | |
| parent | 9962e6fc1a13d37ce475be935b5d0987e9720094 (diff) | |
| download | yosys-9776084eda50060594c6609295c7aa540bb400e1.tar.gz yosys-9776084eda50060594c6609295c7aa540bb400e1.tar.bz2 yosys-9776084eda50060594c6609295c7aa540bb400e1.zip | |
Allow whitebox modules to be overwritten
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 943466ee3..c8ca6d164 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); - if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { + if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str()); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s:%d.\n", |