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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 14:52:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 14:52:04 -0700 |
| commit | 0a1af434e8acfaa692d7990bce68fd23daed9519 (patch) | |
| tree | 3d642131a306e8f9fb3b4a8919649fc72c35a234 /frontends/ast | |
| parent | 08b55a20e36a24d09be9016ceda658bc8ba04ad3 (diff) | |
| download | yosys-0a1af434e8acfaa692d7990bce68fd23daed9519.tar.gz yosys-0a1af434e8acfaa692d7990bce68fd23daed9519.tar.bz2 yosys-0a1af434e8acfaa692d7990bce68fd23daed9519.zip | |
Fix for svinterfaces
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index e4539f303..37a69d8bf 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1398,11 +1398,17 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R has_interfaces = true; } + std::string new_modname = modname; if (has_interfaces) - modname += "$interfaces$" + interf_info; + new_modname += "$interfaces$" + interf_info; - if (!design->has(modname)) { + if (!design->has(new_modname)) { + if (!new_ast) { + auto mod = dynamic_cast<AstModule*>(design->module(modname)); + new_ast = mod->ast->clone(); + } + modname = new_modname; new_ast->str = modname; // Iterate over all interfaces which are ports in this module: |