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* Remove unusedEddie Hung2019-12-301-5/+0
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* Call "proc" if processes inside whiteboxesEddie Hung2019-12-301-1/+1
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-21/+27
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| * write_xaiger: inherit port ordering from original moduleEddie Hung2019-12-271-5/+16
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| * Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"Eddie Hung2019-12-271-19/+27
| | | | | | | | | | This reverts commit 92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing changes made to 3e14ff16676884a1f65cf0eeb0ca9cb1958b8804.
| * Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-271-27/+19
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| | * Revert "write_xaiger: only instantiate each whitebox cell type once"David Shah2019-12-271-27/+19
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| * | write_xaiger: simplify c{i,o}_bitsEddie Hung2019-12-271-12/+6
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| * write_xaiger: only instantiate each whitebox cell type onceEddie Hung2019-12-201-19/+27
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| * Revert "Optimise write_xaiger"Eddie Hung2019-12-201-24/+21
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| * Stray newlineEddie Hung2019-12-061-1/+0
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| * write_xaiger to inst each cell type once, do not call techmap/aigmapEddie Hung2019-12-061-21/+25
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| * Revert "Fold loop"Eddie Hung2019-11-271-3/+6
| | | | | | | | This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35.
| * latch -> boxEddie Hung2019-11-261-1/+1
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| * Fold loopEddie Hung2019-11-261-6/+3
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| * Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-261-1/+1
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| * xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
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* | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-301-2/+3
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* | Really fix it!Eddie Hung2019-12-271-10/+7
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* | write_xaiger: fix arrival times for non boxesEddie Hung2019-12-271-18/+25
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* | write_xaiger to opt instead of just clean whiteboxesEddie Hung2019-12-231-1/+1
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* | Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-171-61/+20
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* | Do not sigmapEddie Hung2019-12-171-1/+1
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* | Revert "Use sigmap signal"Eddie Hung2019-12-171-1/+1
| | | | | | | | This reverts commit 42f990f3a6b7928841fa0e290fa2688925485907.
* | Use sigmap signalEddie Hung2019-12-161-1/+1
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* | Skip $inout transformation if not a PIEddie Hung2019-12-161-3/+5
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* | Revert "write_xaiger: use sigmap bits more consistently"Eddie Hung2019-12-161-4/+5
| | | | | | | | This reverts commit 6c340112fee1bb8989cbd41923aaa627d77d5110.
* | write_xaiger: use sigmap bits more consistentlyEddie Hung2019-12-161-5/+4
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* | Fix writing non-whole modules, including inouts and keepsEddie Hung2019-12-061-90/+81
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* | write_xaiger to support part-selected modules againEddie Hung2019-12-051-11/+37
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* | CleanupEddie Hung2019-12-031-11/+12
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* | write_xaiger to consume abc9_init attribute for abc9_flopsEddie Hung2019-12-031-34/+28
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* | Add comment, use sigmapEddie Hung2019-11-271-2/+2
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* | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
| | | | | | | | This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118.
* | xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
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* | Fold loopEddie Hung2019-11-251-6/+3
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* | Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-251-1/+1
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* | write_xaiger back to working with whole modules onlyEddie Hung2019-11-221-5/+2
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* | Revert "write_xaiger to not use module POs but only write outputs if driven"Eddie Hung2019-11-221-23/+11
| | | | | | | | This reverts commit 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673.
* | write_xaiger to not use module POs but only write outputs if drivenEddie Hung2019-11-211-11/+23
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* | abc9 to support async flops $_DFF_[NP][NP][01]_Eddie Hung2019-11-191-1/+2
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-194-21/+103
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| * write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
| | | | | | | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.
| * Use cell name for btor bad state props when it is a public nameClifford Wolf2019-11-141-9/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add an info string symbol for bad states in btor backendMakai Mann2019-11-111-1/+10
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| * Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
| |\ | | | | | | write_verilog: do not print (*init*) attributes on regs
| | * write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before.
| * | Bugfix in smtio vcd handling of $-identifiersClifford Wolf2019-10-231-6/+9
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Rename $currQ to $abc9_currQEddie Hung2019-10-071-8/+8
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