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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 21:55:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 21:55:56 -0800 |
| commit | 419ca5c207087a1f39d8ec707ec1b94e3a481919 (patch) | |
| tree | 1dce0571bc20702cdd324427b682515dc35f9edc /backends | |
| parent | 6464dc35ec0c57b55aa19345b17eb34f47c15986 (diff) | |
| download | yosys-419ca5c207087a1f39d8ec707ec1b94e3a481919.tar.gz yosys-419ca5c207087a1f39d8ec707ec1b94e3a481919.tar.bz2 yosys-419ca5c207087a1f39d8ec707ec1b94e3a481919.zip | |
Revert "Fold loop"
This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35.
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index a77949b4f..627133314 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -174,7 +174,6 @@ struct XAigerWriter if (bit != wirebit) alias_map[bit] = wirebit; input_bits.insert(wirebit); - undriven_bits.erase(bit); } if (wire->port_output || keep) { @@ -182,8 +181,6 @@ struct XAigerWriter if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); - if (!wire->port_input) - unused_bits.erase(bit); } else log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); @@ -191,6 +188,12 @@ struct XAigerWriter } } + for (auto bit : input_bits) + undriven_bits.erase(sigmap(bit)); + for (auto bit : output_bits) + if (!bit.wire->port_input) + unused_bits.erase(bit); + // TODO: Speed up toposort -- ultimately we care about // box ordering, but not individual AIG cells dict<SigBit, pool<IdString>> bit_drivers, bit_users; |