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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 15:35:19 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 15:37:17 -0800 |
| commit | 3d4644804ea779831b617fe7d12473e3161a93b9 (patch) | |
| tree | 3f3cbb373ef87d430ccd56e65f807cab61c56e05 /backends | |
| parent | 3e14ff16676884a1f65cf0eeb0ca9cb1958b8804 (diff) | |
| download | yosys-3d4644804ea779831b617fe7d12473e3161a93b9.tar.gz yosys-3d4644804ea779831b617fe7d12473e3161a93b9.tar.bz2 yosys-3d4644804ea779831b617fe7d12473e3161a93b9.zip | |
write_xaiger: simplify c{i,o}_bits
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 5729f045a..68d1b1e69 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -81,8 +81,7 @@ struct XAigerWriter pool<SigBit> input_bits, output_bits; dict<SigBit, SigBit> not_map, alias_map; dict<SigBit, pair<SigBit, SigBit>> and_map; - vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits; - vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits; + vector<SigBit> ci_bits, co_bits; dict<SigBit, float> arrival_times; vector<pair<int, int>> aig_gates; @@ -367,7 +366,6 @@ struct XAigerWriter cell->setPort(port_name, rhs); } - int offset = 0; for (auto b : rhs.bits()) { SigBit I = sigmap(b); if (b == RTLIL::Sx) @@ -378,7 +376,7 @@ struct XAigerWriter else alias_map[b] = I; } - co_bits.emplace_back(b, cell, port_name, offset++, 0); + co_bits.emplace_back(b); unused_bits.erase(b); } } @@ -398,9 +396,8 @@ struct XAigerWriter cell->setPort(port_name, rhs); } - int offset = 0; for (const auto &b : rhs.bits()) { - ci_bits.emplace_back(b, cell, port_name, offset++); + ci_bits.emplace_back(b); SigBit O = sigmap(b); if (O != b) alias_map[O] = b; @@ -487,15 +484,13 @@ struct XAigerWriter aig_map[bit] = 2*aig_m; } - for (auto &c : ci_bits) { - RTLIL::SigBit bit = std::get<0>(c); + for (auto bit : ci_bits) { aig_m++, aig_i++; aig_map[bit] = 2*aig_m; } - for (auto &c : co_bits) { - RTLIL::SigBit bit = std::get<0>(c); - std::get<4>(c) = ordered_outputs[bit] = aig_o++; + for (auto bit : co_bits) { + ordered_outputs[bit] = aig_o++; aig_outputs.push_back(bit2aig(bit)); } @@ -508,7 +503,6 @@ struct XAigerWriter ordered_outputs[bit] = aig_o++; aig_outputs.push_back(bit2aig(bit)); } - } void write_aiger(std::ostream &f, bool ascii_mode) |