diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 19:03:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 19:03:02 -0800 |
| commit | 99702efabae4005970bdbae4bbb34c39fdd4c46d (patch) | |
| tree | 6e22f981d724ecd5753634467492324612d5fcdc /backends | |
| parent | 739f5309062f6e60809a2ebe4eda4602cca6fc41 (diff) | |
| download | yosys-99702efabae4005970bdbae4bbb34c39fdd4c46d.tar.gz yosys-99702efabae4005970bdbae4bbb34c39fdd4c46d.tar.bz2 yosys-99702efabae4005970bdbae4bbb34c39fdd4c46d.zip | |
xaiger: do not promote output wires
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 37ef30522..f17a4c775 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -155,11 +155,6 @@ struct XAigerWriter if (wire->port_input) sigmap.add(wire); - // promote output wires - for (auto wire : module->wires()) - if (wire->port_output) - sigmap.add(wire); - for (auto wire : module->wires()) { if (wire->attributes.count("\\init")) { |