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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 19:03:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 21:55:37 -0800 |
| commit | 7136cee6b448cbe5478fd83ee1ca3eaa9f85eeb9 (patch) | |
| tree | 790f0871f996eb8dbcdc562d1da03d734e703202 /backends | |
| parent | 0466c48533ad2831a95c6b63c3a190adb76499e9 (diff) | |
| download | yosys-7136cee6b448cbe5478fd83ee1ca3eaa9f85eeb9.tar.gz yosys-7136cee6b448cbe5478fd83ee1ca3eaa9f85eeb9.tar.bz2 yosys-7136cee6b448cbe5478fd83ee1ca3eaa9f85eeb9.zip | |
xaiger: do not promote output wires
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 46890b071..85136118a 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -153,11 +153,6 @@ struct XAigerWriter if (wire->port_input) sigmap.add(wire); - // promote output wires - for (auto wire : module->wires()) - if (wire->port_output) - sigmap.add(wire); - for (auto wire : module->wires()) { bool keep = wire->attributes.count("\\keep"); |