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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 15:43:37 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 21:57:50 -0800 |
| commit | a30d5e1cc35791a98b2269c5e587c566fe8b0a35 (patch) | |
| tree | 2c431edcd22487842f1b7d45bd276135d14a2d1c /backends | |
| parent | 68717dd03b5a0bfff470cfbc004a43dd431f9236 (diff) | |
| download | yosys-a30d5e1cc35791a98b2269c5e587c566fe8b0a35.tar.gz yosys-a30d5e1cc35791a98b2269c5e587c566fe8b0a35.tar.bz2 yosys-a30d5e1cc35791a98b2269c5e587c566fe8b0a35.zip | |
Fold loop
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 97fec9376..9e5d44470 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -174,6 +174,7 @@ struct XAigerWriter if (bit != wirebit) alias_map[bit] = wirebit; input_bits.insert(wirebit); + undriven_bits.erase(bit); } if (wire->port_output || keep) { @@ -181,6 +182,8 @@ struct XAigerWriter if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); + if (!wire->port_input) + unused_bits.erase(bit); } else log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); @@ -188,12 +191,6 @@ struct XAigerWriter } } - for (auto bit : input_bits) - undriven_bits.erase(sigmap(bit)); - for (auto bit : output_bits) - if (!bit.wire->port_input) - unused_bits.erase(bit); - // TODO: Speed up toposort -- ultimately we care about // box ordering, but not individual AIG cells dict<SigBit, pool<IdString>> bit_drivers, bit_users; |