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* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+2
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-4/+4
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-239-582/+579
* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-161-4/+4
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-4/+40
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-2/+2
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-152-2/+2
* Refactoring of CellType classClifford Wolf2014-08-141-10/+28
* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-021-2/+3
* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-021-3/+19
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-024-5/+5
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-024-19/+19
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-314-86/+86
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-312-4/+8
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-292-338/+0
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-1/+3
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-9/+22
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-281-0/+2
* Using log_assert() instead of assert()Clifford Wolf2014-07-287-11/+5
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-278-22/+22
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-277-14/+14
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-278-14/+14
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-262-35/+35
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-262-3/+3
* Manual fixes for new cell connections APIClifford Wolf2014-07-262-8/+8
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-267-98/+98
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-267-98/+98
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-253-44/+52
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-246-40/+28
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-234-7/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-6/+3
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-232-3/+3
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-232-3/+3
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-222-4/+4
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-228-120/+120
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-228-120/+120
* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-211-1/+14
* Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...Clifford Wolf2014-07-201-17/+21
* Added support for $bu0 to verilog backendClifford Wolf2014-07-201-0/+16
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-131-0/+1
* Use log_abort() and log_assert() in BTOR backendClifford Wolf2014-03-071-18/+17
* Added $lut support to blif backend (by user eddiehung from reddit)Clifford Wolf2014-02-221-0/+23
* Better handling of nameDef and nameRef in edif backendClifford Wolf2014-02-211-21/+27
* Fixed instantiating multi-bit ports in edif backendClifford Wolf2014-02-211-2/+4
* Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -paramClifford Wolf2014-02-211-17/+65
* modified btor synthesis script for correct use of splice command.Ahmed Irfan2014-02-122-6/+6
* disabling splice command in the scriptAhmed Irfan2014-02-112-2/+6
* register output correctedAhmed Irfan2014-02-111-1/+1
* added concat and slice cell translationAhmed Irfan2014-02-113-36/+59
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+22