Using log_assert() instead of assert()

7 files changed, 5 insertions, 11 deletions

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 2b783e734..d167c3f4e 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -27,7 +27,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 struct BlifDumperConfig
 {
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 4af121005..f721fdc99 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -549,7 +549,7 @@ struct BtorDumper
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
+				//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
 				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
 				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 5eff4598a..49f719a4a 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -26,7 +26,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index d45e94a09..87a3d6cb3 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -27,7 +27,6 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 #include <string.h>
 #include <errno.h>
 
@@ -41,7 +40,7 @@ void ILANG_BACKEND::dump_const(FILE *f, const RTLIL::Const &data, int width, int
 		if (width == 32 && autoint) {
 			int32_t val = 0;
 			for (int i = 0; i < width; i++) {
-				assert(offset+i < (int)data.bits.size());
+				log_assert(offset+i < (int)data.bits.size());
 				switch (data.bits[offset+i]) {
 				case RTLIL::S0: break;
 				case RTLIL::S1: val |= 1 << i; break;
@@ -55,7 +54,7 @@ void ILANG_BACKEND::dump_const(FILE *f, const RTLIL::Const &data, int width, int
 		}
 		fprintf(f, "%d'", width);
 		for (int i = offset+width-1; i >= offset; i--) {
-			assert(i < (int)data.bits.size());
+			log_assert(i < (int)data.bits.size());
 			switch (data.bits[i]) {
 			case RTLIL::S0: fprintf(f, "0"); break;
 			case RTLIL::S1: fprintf(f, "1"); break;
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 2f94e290d..9faed77c9 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -23,7 +23,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 
 static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 283448c3b..ab5316ec3 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -23,7 +23,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
 {
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index f7f0ecaf4..fe2c2b247 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -30,7 +30,6 @@
 #include "kernel/register.h"
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
-#include <assert.h>
 #include <string>
 #include <sstream>
 #include <set>
@@ -161,7 +160,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
 		if (width == 32 && !no_decimal) {
 			int32_t val = 0;
 			for (int i = offset+width-1; i >= offset; i--) {
-				assert(i < (int)data.bits.size());
+				log_assert(i < (int)data.bits.size());
 				if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
 					goto dump_bits;
 				if (data.bits[i] == RTLIL::S1)
@@ -175,7 +174,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
 			if (width == 0)
 				fprintf(f, "0");
 			for (int i = offset+width-1; i >= offset; i--) {
-				assert(i < (int)data.bits.size());
+				log_assert(i < (int)data.bits.size());
 				switch (data.bits[i]) {
 				case RTLIL::S0: fprintf(f, "0"); break;
 				case RTLIL::S1: fprintf(f, "1"); break;