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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-02 21:54:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-02 21:54:02 +0200 |
| commit | 88cf00ce7874ec7951b09d85e959dd2c6ed261b6 (patch) | |
| tree | a12e6d0156048212c00c110c967a451fc0ed7236 /backends | |
| parent | ca1b5d50e0e577a88ae265b71679b81e71980db8 (diff) | |
| download | yosys-88cf00ce7874ec7951b09d85e959dd2c6ed261b6.tar.gz yosys-88cf00ce7874ec7951b09d85e959dd2c6ed261b6.tar.bz2 yosys-88cf00ce7874ec7951b09d85e959dd2c6ed261b6.zip | |
Be more conservative with printing decimal numbers in verilog backend
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index c691eae60..605616b31 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -163,11 +163,12 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = log_assert(i < (int)data.bits.size()); if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1) goto dump_bits; + if (data.bits[i] == RTLIL::S1 && (i - offset) == 31) + goto dump_bits; if (data.bits[i] == RTLIL::S1) val |= 1 << (i - offset); } - // fprintf(f, "%s32'sd%u", val < 0 ? "-" : "", abs(val)); - fprintf(f, "%d", val); + fprintf(f, "32'%sd%d", set_signed ? "s" : "", val); } else { dump_bits: fprintf(f, "%d'%sb", width, set_signed ? "s" : ""); |