Replaced more old SigChunk programming patterns

6 files changed, 28 insertions, 40 deletions

diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index 028d1f37a..db49880ae 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -119,10 +119,9 @@ static void autotest(FILE *f, RTLIL::Design *design)
 					if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
 						continue;
 					RTLIL::SigSpec &signal = (*it4)->signal;
-					for (size_t i = 0; i < signal.chunks().size(); i++) {
-						if (signal.chunks()[i].wire == wire)
+					for (auto &c : signal.chunks())
+						if (c.wire == wire)
 							is_clksignal = true;
-					}
 				}
 				if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
 					signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index d0c250790..fc090cfe0 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -68,20 +68,18 @@ struct BlifDumper
 		return cstr_buf.back().c_str();
 	}
 
-	const char *cstr(RTLIL::SigSpec sig)
+	const char *cstr(RTLIL::SigBit sig)
 	{
-		log_assert(sig.size() == 1);
+		if (sig.wire == NULL)
+			return sig == RTLIL::State::S1 ?  "$true" : "$false";
 
-		if (sig.chunks().at(0).wire == NULL)
-			return sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1 ?  "$true" : "$false";
-
-		std::string str = RTLIL::unescape_id(sig.chunks().at(0).wire->name);
+		std::string str = RTLIL::unescape_id(sig.wire->name);
 		for (size_t i = 0; i < str.size(); i++)
 			if (str[i] == '#' || str[i] == '=')
 				str[i] = '?';
 
-		if (sig.chunks().at(0).wire->width != 1)
-			str += stringf("[%d]", sig.chunks().at(0).offset);
+		if (sig.wire->width != 1)
+			str += stringf("[%d]", sig.offset);
 
 		cstr_buf.push_back(str);
 		return cstr_buf.back().c_str();
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 8f36f4090..a3ae9649e 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -314,12 +314,9 @@ struct EdifBackend : public Backend {
 				}
 			}
 			for (auto &it : net_join_db) {
-				RTLIL::SigSpec sig = it.first;
-				log_assert(sig.size() == 1);
-				if (sig.chunks().at(0).wire == NULL) {
-					if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1)
-						continue;
-				}
+				RTLIL::SigBit sig = it.first;
+				if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
+					continue;
 				std::string netname = log_signal(sig);
 				for (size_t i = 0; i < netname.size(); i++)
 					if (netname[i] == ' ' || netname[i] == '\\')
@@ -327,10 +324,10 @@ struct EdifBackend : public Backend {
 				fprintf(f, "          (net %s (joined\n", EDIF_DEF(netname));
 				for (auto &ref : it.second)
 					fprintf(f, "            %s\n", ref.c_str());
-				if (sig.chunks().at(0).wire == NULL) {
-					if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0)
+				if (sig.wire == NULL) {
+					if (sig == RTLIL::State::S0)
 						fprintf(f, "            (portRef G (instanceRef GND))\n");
-					if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1)
+					if (sig == RTLIL::State::S1)
 						fprintf(f, "            (portRef P (instanceRef VCC))\n");
 				}
 				fprintf(f, "          ))\n");
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index a312b02ce..e3093e378 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -103,7 +103,7 @@ void ILANG_BACKEND::dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool au
 void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint)
 {
 	if (sig.chunks().size() == 1) {
-		dump_sigchunk(f, sig.chunks()[0], autoint);
+		dump_sigchunk(f, sig.chunks().front(), autoint);
 	} else {
 		fprintf(f, "{ ");
 		for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index a4cad5add..b2e472bf3 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -28,23 +28,19 @@
 
 static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
 {
-	if (sig.chunks().size() != 1)
-error:
+	if (!sig.is_fully_const() && !sig.is_wire())
 		log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
 
 	conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
 
-	if (sig.chunks()[0].wire == NULL) {
+	if (sig.is_fully_const()) {
 		celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.size(), sig.size(), sig.size()));
-		constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.size(), sig.chunks()[0].data.as_int(),
-				sig.size(), sig.size(), sig.chunks()[0].data.as_int(), sig.chunks()[0].data.as_int()));
-		return stringf("CONST_%d_0x%x", sig.size(), sig.chunks()[0].data.as_int());
+		constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n",
+				sig.size(), sig.as_int(), sig.size(), sig.size(), sig.as_int(), sig.as_int()));
+		return stringf("CONST_%d_0x%x", sig.size(), sig.as_int());
 	}
 
-	if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width)
-		goto error;
-
-	return RTLIL::unescape_id(sig.chunks()[0].wire->name);
+	return RTLIL::unescape_id(sig.as_wire()->name);
 }
 
 struct IntersynthBackend : public Backend {
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 8e894cafd..e548df361 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -25,18 +25,17 @@
 #include <string>
 #include <assert.h>
 
-static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
+static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
 {
-	log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1);
-	if (s.chunks()[0].wire) {
-		if (s.chunks()[0].wire->width > 1)
-			fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset);
+	if (s.wire) {
+		if (s.wire->width > 1)
+			fprintf(f, " %s[%d]", RTLIL::id2cstr(s.wire->name), s.offset);
 		else
-			fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name));
+			fprintf(f, " %s", RTLIL::id2cstr(s.wire->name));
 	} else {
-		if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0)
+		if (s == RTLIL::State::S0)
 			fprintf(f, " %s", neg.c_str());
-		else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1)
+		else if (s == RTLIL::State::S1)
 			fprintf(f, " %s", pos.c_str());
 		else
 			fprintf(f, " %s%d", ncpf.c_str(), nc_counter++);
@@ -92,7 +91,6 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 		for (auto &sig : port_sigs) {
 			for (int i = 0; i < sig.size(); i++) {
 				RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1);
-				log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1);
 				print_spice_net(f, s, neg, pos, ncpf, nc_counter);
 			}
 		}