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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
| commit | f092b5014895dc5dc62b8103fcedf94cfa9f85a8 (patch) | |
| tree | 2f09add560746030249fe333e551de2f113bccdb /backends | |
| parent | bf486002d9a6d976b3d086700ccdcfb0fb70ba0b (diff) | |
| download | yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.gz yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.bz2 yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.zip | |
Renamed $_INV_ cell type to $_NOT_
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/blif/blif.cc | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 5daab6691..386d68d8b 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -143,7 +143,7 @@ struct BlifDumper { RTLIL::Cell *cell = cell_it.second; - if (!config->icells_mode && cell->type == "$_INV_") { + if (!config->icells_mode && cell->type == "$_NOT_") { fprintf(f, ".names %s %s\n0 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y"))); continue; diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index cafc1f3f0..81c938bdd 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -370,7 +370,7 @@ void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell) { - if (cell->type == "$_INV_") { + if (cell->type == "$_NOT_") { fprintf(f, "%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort("\\Y")); fprintf(f, " = "); |