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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:48:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:52:55 +0200 |
| commit | ec923652e2eb721aa16657e54a67666f855c3d65 (patch) | |
| tree | 934ce8ee55c3c58a1e2c11f19eec194665413906 /backends | |
| parent | a8d3a68971ccc4e47c54a906aae374a9a54b1415 (diff) | |
| download | yosys-ec923652e2eb721aa16657e54a67666f855c3d65.tar.gz yosys-ec923652e2eb721aa16657e54a67666f855c3d65.tar.bz2 yosys-ec923652e2eb721aa16657e54a67666f855c3d65.zip | |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/blif/blif.cc | 4 | ||||
| -rw-r--r-- | backends/edif/edif.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index edb6809ee..a240d2a26 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -118,7 +118,7 @@ struct BlifDumper for (auto &it : inputs) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) - fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i))); + fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i))); } fprintf(f, "\n"); @@ -126,7 +126,7 @@ struct BlifDumper for (auto &it : outputs) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) - fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i))); + fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i))); } fprintf(f, "\n"); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index f003c750d..74cf24997 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -271,7 +271,7 @@ struct EdifBackend : public Backend { } else { fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir); for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i)); + RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); } } |