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Age
Files
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*
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parse_xaiger to not take box_lookup
Eddie Hung
2019-12-31
1
-2
/
+13
*
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Do not re-order carry chain ports, just precompute iteration order
Eddie Hung
2019-12-31
1
-22
/
+32
*
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write_xaiger: be more precise with ff_bits, remove ff_aig_map
Eddie Hung
2019-12-31
1
-21
/
+19
*
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Retry getting rid of write_xaiger's holes_mode
Eddie Hung
2019-12-31
1
-81
/
+41
*
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Revert "Get rid of holes_mode"
Eddie Hung
2019-12-30
1
-35
/
+70
*
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Get rid of holes_mode
Eddie Hung
2019-12-30
1
-70
/
+35
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/
*
write_xaiger to use scratchpad for stats; cleanup abc9
Eddie Hung
2019-12-30
1
-17
/
+5
*
Remove unused
Eddie Hung
2019-12-30
1
-5
/
+0
*
Call "proc" if processes inside whiteboxes
Eddie Hung
2019-12-30
1
-1
/
+1
*
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-30
1
-21
/
+27
|
\
|
*
write_xaiger: inherit port ordering from original module
Eddie Hung
2019-12-27
1
-5
/
+16
|
*
Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"
Eddie Hung
2019-12-27
1
-19
/
+27
|
*
Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung
2019-12-27
1
-27
/
+19
|
|
\
|
|
*
Revert "write_xaiger: only instantiate each whitebox cell type once"
David Shah
2019-12-27
1
-27
/
+19
|
*
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write_xaiger: simplify c{i,o}_bits
Eddie Hung
2019-12-27
1
-12
/
+6
|
|
/
|
*
write_xaiger: only instantiate each whitebox cell type once
Eddie Hung
2019-12-20
1
-19
/
+27
|
*
Revert "Optimise write_xaiger"
Eddie Hung
2019-12-20
1
-24
/
+21
|
*
Stray newline
Eddie Hung
2019-12-06
1
-1
/
+0
|
*
write_xaiger to inst each cell type once, do not call techmap/aigmap
Eddie Hung
2019-12-06
1
-21
/
+25
|
*
Revert "Fold loop"
Eddie Hung
2019-11-27
1
-3
/
+6
|
*
latch -> box
Eddie Hung
2019-11-26
1
-1
/
+1
|
*
Fold loop
Eddie Hung
2019-11-26
1
-6
/
+3
|
*
Do not sigmap keep bits inside write_xaiger
Eddie Hung
2019-11-26
1
-1
/
+1
|
*
xaiger: do not promote output wires
Eddie Hung
2019-11-26
1
-5
/
+0
*
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Add "synth_xilinx -dff" option, cleanup abc9
Eddie Hung
2019-12-30
1
-2
/
+3
*
|
Really fix it!
Eddie Hung
2019-12-27
1
-10
/
+7
*
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write_xaiger: fix arrival times for non boxes
Eddie Hung
2019-12-27
1
-18
/
+25
*
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write_xaiger to opt instead of just clean whiteboxes
Eddie Hung
2019-12-23
1
-1
/
+1
*
|
Cleanup xaiger, remove unnecessary complexity with inout
Eddie Hung
2019-12-17
1
-61
/
+20
*
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Do not sigmap
Eddie Hung
2019-12-17
1
-1
/
+1
*
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Revert "Use sigmap signal"
Eddie Hung
2019-12-17
1
-1
/
+1
*
|
Use sigmap signal
Eddie Hung
2019-12-16
1
-1
/
+1
*
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Skip $inout transformation if not a PI
Eddie Hung
2019-12-16
1
-3
/
+5
*
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Revert "write_xaiger: use sigmap bits more consistently"
Eddie Hung
2019-12-16
1
-4
/
+5
*
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write_xaiger: use sigmap bits more consistently
Eddie Hung
2019-12-16
1
-5
/
+4
*
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Fix writing non-whole modules, including inouts and keeps
Eddie Hung
2019-12-06
1
-90
/
+81
*
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write_xaiger to support part-selected modules again
Eddie Hung
2019-12-05
1
-11
/
+37
*
|
Cleanup
Eddie Hung
2019-12-03
1
-11
/
+12
*
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write_xaiger to consume abc9_init attribute for abc9_flops
Eddie Hung
2019-12-03
1
-34
/
+28
*
|
Add comment, use sigmap
Eddie Hung
2019-11-27
1
-2
/
+2
*
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Revert "Fold loop"
Eddie Hung
2019-11-27
1
-3
/
+6
*
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xaiger: do not promote output wires
Eddie Hung
2019-11-26
1
-5
/
+0
*
|
Fold loop
Eddie Hung
2019-11-25
1
-6
/
+3
*
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Do not sigmap keep bits inside write_xaiger
Eddie Hung
2019-11-25
1
-1
/
+1
*
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write_xaiger back to working with whole modules only
Eddie Hung
2019-11-22
1
-5
/
+2
*
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Revert "write_xaiger to not use module POs but only write outputs if driven"
Eddie Hung
2019-11-22
1
-23
/
+11
*
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write_xaiger to not use module POs but only write outputs if driven
Eddie Hung
2019-11-21
1
-11
/
+23
*
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abc9 to support async flops $_DFF_[NP][NP][01]_
Eddie Hung
2019-11-19
1
-1
/
+2
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-19
4
-21
/
+103
|
\
|
|
*
write_verilog: add -extmem option, to write split memory init files.
whitequark
2019-11-18
1
-10
/
+80
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