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| * | | | | Preserve topo ordering from -prep_holes to write_xaigerEddie Hung2020-01-031-159/+77
| * | | | | WIPEddie Hung2020-01-031-67/+8
| * | | | | WIPEddie Hung2020-01-031-23/+141
| * | | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2020-01-021-145/+128
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| * | | | | | Move Pass::call() out of abc9_ops into abc9Eddie Hung2019-12-301-0/+4
| * | | | | | CleanupEddie Hung2019-12-301-7/+3
| * | | | | | Rid unnecessary ifEddie Hung2019-12-301-13/+11
| * | | | | | Get rid of holes_modeEddie Hung2019-12-301-70/+35
| * | | | | | Add abc9_ops -prep_holesEddie Hung2019-12-301-132/+8
* | | | | | | Improve yosys-smtbmc "solver not found" handlingClaire Wolf2020-01-271-1/+5
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* | | | | | Merge pull request #1629 from YosysHQ/mwk/edif-zClaire Wolf2020-01-211-0/+2
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| * | | | | edif: Just ignore connections to 'zMarcin Kościelnicki2020-01-131-0/+2
* | | | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-141-25/+37
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| * | | | | remove whitespaceMiodrag Milanovic2020-01-101-1/+1
| * | | | | Export wire properties as well in EDIFMiodrag Milanovic2020-01-101-26/+38
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* | | | | write_xaiger: create holes_sigmap before modificationsEddie Hung2020-01-111-1/+2
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* | | | write_xaiger: sort holes by offset as well as port_idEddie Hung2020-01-111-1/+2
* | | | write_xaiger: cleanup holes generationEddie Hung2020-01-081-80/+89
* | | | write_xaiger: holes PIs only if whiteboxEddie Hung2020-01-081-13/+18
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* | | write_xaiger: make more robust, update docEddie Hung2020-01-061-29/+14
* | | write_aiger: make more robustEddie Hung2020-01-061-0/+8
* | | Restore write_xaiger's holes_mode since port_id order causes QoREddie Hung2020-01-031-27/+19
* | | CleanupEddie Hung2020-01-021-2/+1
* | | write_xaiger: get rid of external_bits dictEddie Hung2020-01-021-1/+1
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* | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-021-89/+47
* | Get rid of (* abc9_keep *) in write_xaiger tooEddie Hung2020-01-011-15/+18
* | attributes.count() -> get_bool_attribute()Eddie Hung2020-01-011-1/+1
* | parse_xaiger to not take box_lookupEddie Hung2019-12-311-2/+13
* | Do not re-order carry chain ports, just precompute iteration orderEddie Hung2019-12-311-22/+32
* | write_xaiger: be more precise with ff_bits, remove ff_aig_mapEddie Hung2019-12-311-21/+19
* | Retry getting rid of write_xaiger's holes_modeEddie Hung2019-12-311-81/+41
* | Revert "Get rid of holes_mode"Eddie Hung2019-12-301-35/+70
* | Get rid of holes_modeEddie Hung2019-12-301-70/+35
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* write_xaiger to use scratchpad for stats; cleanup abc9Eddie Hung2019-12-301-17/+5
* Remove unusedEddie Hung2019-12-301-5/+0
* Call "proc" if processes inside whiteboxesEddie Hung2019-12-301-1/+1
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-21/+27
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| * write_xaiger: inherit port ordering from original moduleEddie Hung2019-12-271-5/+16
| * Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"Eddie Hung2019-12-271-19/+27
| * Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-12-271-27/+19
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| | * Revert "write_xaiger: only instantiate each whitebox cell type once"David Shah2019-12-271-27/+19
| * | write_xaiger: simplify c{i,o}_bitsEddie Hung2019-12-271-12/+6
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| * write_xaiger: only instantiate each whitebox cell type onceEddie Hung2019-12-201-19/+27
| * Revert "Optimise write_xaiger"Eddie Hung2019-12-201-24/+21
| * Stray newlineEddie Hung2019-12-061-1/+0
| * write_xaiger to inst each cell type once, do not call techmap/aigmapEddie Hung2019-12-061-21/+25
| * Revert "Fold loop"Eddie Hung2019-11-271-3/+6
| * latch -> boxEddie Hung2019-11-261-1/+1
| * Fold loopEddie Hung2019-11-261-6/+3
| * Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-261-1/+1