diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 17:25:32 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 17:25:32 -0800 |
| commit | 58ab9f6021bc5b90956d97759ef0f3bc8c7e209e (patch) | |
| tree | ef62195d9eef5a695f1905c1e9e56374aa48ddf3 /backends | |
| parent | 04a2eb82045a658de22cea610a3ac8c5dee9333c (diff) | |
| download | yosys-58ab9f6021bc5b90956d97759ef0f3bc8c7e209e.tar.gz yosys-58ab9f6021bc5b90956d97759ef0f3bc8c7e209e.tar.bz2 yosys-58ab9f6021bc5b90956d97759ef0f3bc8c7e209e.zip | |
write_xaiger: create holes_sigmap before modifications
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7ee5058ae..a6c87159d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -771,6 +771,8 @@ struct XAigerWriter // created a new $paramod ... Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap"); + SigMap holes_sigmap(holes_module); + dict<SigSpec, SigSpec> replace; for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) { auto cell = it->second; @@ -808,7 +810,6 @@ struct XAigerWriter ++it; } - SigMap holes_sigmap(holes_module); for (auto &conn : holes_module->connections_) { auto it = replace.find(sigmap(conn.second)); if (it != replace.end()) |