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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 19:23:54 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 19:23:54 -0800 |
| commit | b42b64e8ed713b0e9810f18db7cafcf356e2b4f6 (patch) | |
| tree | 2fadbedfb29c35e246b2cc2972c7a9d0ae1e8c6c /backends | |
| parent | 88334cab891d47778931c1ea0060fd107052e189 (diff) | |
| download | yosys-b42b64e8ed713b0e9810f18db7cafcf356e2b4f6.tar.gz yosys-b42b64e8ed713b0e9810f18db7cafcf356e2b4f6.tar.bz2 yosys-b42b64e8ed713b0e9810f18db7cafcf356e2b4f6.zip | |
Move Pass::call() out of abc9_ops into abc9
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 9e0a56963..830c86787 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -710,6 +710,10 @@ struct XAigerWriter RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str())); log_assert(holes_module); + for (auto cell : holes_module->cells()) + if (!cell->type.in("$_NOT_", "$_AND_")) + log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n"); + module->design->selection_stack.emplace_back(false); module->design->selection().select(holes_module); |