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author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 18:49:33 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 18:49:33 -0800 |
commit | 88334cab891d47778931c1ea0060fd107052e189 (patch) | |
tree | 6562f5773e478a48c6f70df3f96cace717ec25e4 /backends | |
parent | 52f649dcfd2bba3e4efc219b53e7937281a658c6 (diff) | |
download | yosys-88334cab891d47778931c1ea0060fd107052e189.tar.gz yosys-88334cab891d47778931c1ea0060fd107052e189.tar.bz2 yosys-88334cab891d47778931c1ea0060fd107052e189.zip |
Cleanup
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 35fb8d5dc..9e0a56963 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -645,19 +645,12 @@ struct XAigerWriter // write_o_buffer(0); if (!box_list.empty() || !ff_bits.empty()) { - RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str())); - log_assert(holes_module); - - dict<IdString, Cell*> cell_cache; - int box_count = 0; for (auto cell : box_list) { RTLIL::Module* orig_box_module = module->design->module(cell->type); log_assert(orig_box_module); IdString derived_name = orig_box_module->derive(module->design, cell->parameters); RTLIL::Module* box_module = module->design->module(derived_name); - if (box_module->has_processes()) - Pass::call_on_module(module->design, box_module, "proc"); int box_inputs = 0, box_outputs = 0; // NB: Assume box_module->ports are sorted alphabetically @@ -714,6 +707,9 @@ struct XAigerWriter f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be)); f.write(buffer_str.data(), buffer_str.size()); + RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str())); + log_assert(holes_module); + module->design->selection_stack.emplace_back(false); module->design->selection().select(holes_module); |