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backends
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verilog
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Author
Age
Files
Lines
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-1
/
+1
*
write_verilog: handle the $shift cell.
whitequark
2018-12-16
1
-0
/
+29
*
Merge pull request #736 from whitequark/select_assert_list
Clifford Wolf
2018-12-16
1
-1
/
+1
|
\
|
*
write_verilog: add a missing newline.
whitequark
2018-12-16
1
-1
/
+1
*
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write_verilog: correctly map RTLIL `sync init`.
whitequark
2018-12-07
1
-0
/
+2
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/
*
adding offset info to memories
rafaeltp
2018-10-18
1
-1
/
+1
*
adding offset info to memories
rafaeltp
2018-10-18
1
-2
/
+3
*
Fixed typo in "verilog_write" help message
acw1251
2018-09-18
1
-3
/
+3
*
Add $lut support to Verilog back-end
Clifford Wolf
2018-09-06
1
-0
/
+13
*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-2
/
+2
*
Add $dlatch support to write_verilog
Clifford Wolf
2018-04-22
1
-0
/
+38
*
Add $shiftx support to verilog front-end
Clifford Wolf
2017-10-07
1
-0
/
+17
*
Rename "write_verilog -nobasenradix" to "write_verilog -decimal"
Clifford Wolf
2017-10-03
1
-16
/
+13
*
Fixed wrong declaration in Verilog backend
dh73
2017-10-01
1
-3
/
+3
*
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...
dh73
2017-10-01
1
-3
/
+16
*
Add $_ANDNOT_ and $_ORNOT_ gates
Clifford Wolf
2017-05-17
1
-4
/
+6
*
Cleanups and fixed in write_verilog regarding reg init
Clifford Wolf
2016-11-16
1
-15
/
+61
*
Added hex constant support to write_verilog
Clifford Wolf
2016-11-03
1
-4
/
+62
*
Adde "write_verilog -renameprefix -v"
Clifford Wolf
2016-11-01
1
-5
/
+23
*
Bugfix in partial mem write handling in verilog back-end
Clifford Wolf
2016-08-20
1
-42
/
+26
*
Added missing support for mem read enable ports to verilog back-end
Clifford Wolf
2016-08-18
1
-6
/
+14
*
Fixed upto handling in verilog back-end
Clifford Wolf
2016-08-15
1
-0
/
+3
*
Added "write_verilog -defparam"
Clifford Wolf
2016-07-30
1
-2
/
+21
*
Added "write_verilog -nodec -nostr"
Clifford Wolf
2016-07-30
1
-4
/
+27
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
1
-1
/
+1
*
Bugfix in write_verilog for RTLIL processes
Clifford Wolf
2016-03-14
1
-9
/
+20
*
Bugfixes in writing of memories as Verilog
Clifford Wolf
2015-09-25
1
-7
/
+8
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
1
-2
/
+2
*
Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
1
-3
/
+3
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
1
-1
/
+1
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-4
/
+4
*
$mem cell in verilog backend : grouped writes by clock
luke whittlesey
2015-06-08
1
-54
/
+108
*
Bug fix in $mem verilog backend + changed tests/bram flow of make test.
luke whittlesey
2015-06-04
1
-14
/
+16
*
Some fixes for $mem in verilog back-end
Clifford Wolf
2015-05-20
1
-19
/
+23
*
Merge pull request #63 from wluker/verilog-backend-mem
Clifford Wolf
2015-05-11
1
-1
/
+2
|
\
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*
Fixed bug in $mem cell verilog code generation.
luke whittlesey
2015-05-11
1
-11
/
+12
*
|
Disabled broken $mem support in verilog backend
Clifford Wolf
2015-05-10
1
-11
/
+11
|
/
*
Made changes recommended by Clifford Wolf ...
luke whittlesey
2015-05-10
1
-22
/
+11
*
Verilog backend for $mem cells should now be able to handle different
luke whittlesey
2015-05-08
1
-50
/
+105
*
Added support for $mem cells in the verilog backend.
luke whittlesey
2015-05-07
1
-1
/
+120
*
Minor fixes in handling of "init" attribute
Clifford Wolf
2015-04-09
1
-7
/
+7
*
Added "init" attribute support to verilog backend
Clifford Wolf
2015-04-04
1
-0
/
+5
*
Added Verilog backend $dffsr support
Clifford Wolf
2015-03-18
1
-1
/
+51
*
Fixed "write_verilog -attr2comment" handling of "*/" in strings
Clifford Wolf
2015-02-13
1
-2
/
+4
*
Added dict/pool.sort()
Clifford Wolf
2015-01-24
1
-0
/
+2
*
Cosmetic changes in verilog output format
Clifford Wolf
2015-01-02
1
-5
/
+10
*
Replaced std::unordered_map as implementation for Yosys::dict
Clifford Wolf
2014-12-26
1
-25
/
+25
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
1
-1
/
+1
*
Added $dffe support to write_verilog
Clifford Wolf
2014-12-20
1
-3
/
+14
*
Fixed generation of temp names in verilog backend
Clifford Wolf
2014-11-07
1
-4
/
+5
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