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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-25 13:49:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-25 13:49:26 +0200 |
| commit | 4ac202e2a5b07a610deb43a667ea3a66d95241d4 (patch) | |
| tree | 050342b0849beded4ecc8cc6369f2387a35c32f8 /backends/verilog | |
| parent | b2544cfcf77c3a7e923d05151a8e37b079559119 (diff) | |
| download | yosys-4ac202e2a5b07a610deb43a667ea3a66d95241d4.tar.gz yosys-4ac202e2a5b07a610deb43a667ea3a66d95241d4.tar.bz2 yosys-4ac202e2a5b07a610deb43a667ea3a66d95241d4.zip | |
Bugfixes in writing of memories as Verilog
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index c04389f63..10f10e3cd 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -165,12 +165,13 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o log_assert(i < (int)data.bits.size()); if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1) goto dump_bits; - if (data.bits[i] == RTLIL::S1 && (i - offset) == 31) - goto dump_bits; if (data.bits[i] == RTLIL::S1) val |= 1 << (i - offset); } - f << stringf("32'%sd %d", set_signed ? "s" : "", val); + if (set_signed && val < 0) + f << stringf("-32'sd %u", -val); + else + f << stringf("32'%sd %u", set_signed ? "s" : "", val); } else { dump_bits: f << stringf("%d'%sb", width, set_signed ? "s" : ""); @@ -805,15 +806,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) // initial begin // memid[0] <= ... // end - int mem_val; f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size-1, 0); if (use_init) { f << stringf("%s" "initial begin\n", indent.c_str()); for (int i=0; i<size; i++) { - mem_val = cell->parameters["\\INIT"].extract(i*width, width).as_int(); - f << stringf("%s" " %s[%d] <= %d'd%d;\n", indent.c_str(), mem_id.c_str(), i, width, mem_val); + f << stringf("%s" " %s[%d] <= ", indent.c_str(), mem_id.c_str(), i); + dump_const(f, cell->parameters["\\INIT"].extract(i*width, width)); + f << stringf(";\n"); } f << stringf("%s" "end\n", indent.c_str()); } @@ -884,7 +885,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) std::ostringstream os; dump_sigspec(os, sig_rd_data); std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str()); - clk_to_lof_body[clk_domain_str].push_back(line); + clk_to_lof_body[""].push_back(line); } } else { // for non-clocked read-ports make something like: |