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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-04 18:06:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-04 18:06:52 +0200 |
| commit | b0c0ede879341c0beeae4a9a5e8578da12f3b3f1 (patch) | |
| tree | d9b78146e339b35d4eaf0e096aa203deb9a93702 /backends/verilog | |
| parent | 0737bf5fb8d82427bc463582ce9e84c4109a7829 (diff) | |
| download | yosys-b0c0ede879341c0beeae4a9a5e8578da12f3b3f1.tar.gz yosys-b0c0ede879341c0beeae4a9a5e8578da12f3b3f1.tar.bz2 yosys-b0c0ede879341c0beeae4a9a5e8578da12f3b3f1.zip | |
Added "init" attribute support to verilog backend
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index ba57e8814..0d667c638 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -299,6 +299,11 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); else if (!wire->port_input && !wire->port_output) f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); + if (wire->attributes.count("\\init")) { + f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str()); + dump_const(f, wire->attributes.at("\\init")); + f << stringf(";\n"); + } #endif } |