| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | | | | | | | | | | | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 | |
| | * | | | | | | | | | | | | | | | | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | shregmap -tech xilinx to delete $shiftx for var length SRL | Eddie Hung | 2019-03-19 | 1 | -10/+3 | |
| | * | | | | | | | | | | | | | | | | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 53 | -38/+2398 | |
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| | * | | | | | | | | | | | | | | | | | Make output port a non chain user | Eddie Hung | 2019-03-19 | 1 | -2/+4 | |
| | * | | | | | | | | | | | | | | | | | Fix shregmap to correctly recognise non chain users; cleanup | Eddie Hung | 2019-03-18 | 1 | -17/+15 | |
| | * | | | | | | | | | | | | | | | | | shiftx NULL pointer check | Eddie Hung | 2019-03-18 | 1 | -8/+10 | |
| | * | | | | | | | | | | | | | | | | | Cleanup | Eddie Hung | 2019-03-16 | 1 | -35/+25 | |
| | * | | | | | | | | | | | | | | | | | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 2 | -13/+18 | |
| | * | | | | | | | | | | | | | | | | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 | |
| | * | | | | | | | | | | | | | | | | | Working | Eddie Hung | 2019-03-15 | 3 | -274/+434 | |
| | * | | | | | | | | | | | | | | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 | |
| | * | | | | | | | | | | | | | | | | | Misspell | Eddie Hung | 2019-03-14 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | Revert "Add shregmap -init_msb_first and use in synth_xilinx" | Eddie Hung | 2019-03-14 | 2 | -17/+4 | |
| | * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 82 | -584/+2483 | |
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| | * | | | | | | | | | | | | | | | | | | Add shregmap -init_msb_first and use in synth_xilinx | Eddie Hung | 2019-03-14 | 2 | -4/+16 | |
| | * | | | | | | | | | | | | | | | | | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
| | * | | | | | | | | | | | | | | | | | | Move shregmap until after first techmap | Eddie Hung | 2019-03-13 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
| | * | | | | | | | | | | | | | | | | | | Remove SRL16/32 from cells_xtra | Eddie Hung | 2019-02-28 | 2 | -18/+2 | |
| | * | | | | | | | | | | | | | | | | | | Add SRL16 and SRL32 sim models | Eddie Hung | 2019-02-28 | 1 | -0/+39 | |
| | * | | | | | | | | | | | | | | | | | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
| | * | | | | | | | | | | | | | | | | | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 2 | -24/+29 | |
| | * | | | | | | | | | | | | | | | | | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 2 | -22/+19 | |
| | * | | | | | | | | | | | | | | | | | | synth_xilinx to now have shregmap call after dff2dffe | Eddie Hung | 2019-02-28 | 1 | -0/+2 | |
| | * | | | | | | | | | | | | | | | | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
| * | | | | | | | | | | | | | | | | | | | Merge pull request #952 from YosysHQ/clifford/fix370 | Clifford Wolf | 2019-04-22 | 1 | -3/+18 | |
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| | * | | | | | | | | | | | | | | | | | | | Determine correct signedness and expression width in for loop unrolling, fixe... | Clifford Wolf | 2019-04-22 | 1 | -3/+18 | |
| * | | | | | | | | | | | | | | | | | | | | Merge pull request #951 from YosysHQ/clifford/logdebug | Clifford Wolf | 2019-04-22 | 11 | -53/+183 | |
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| | * | | | | | | | | | | | | | | | | | | | | Add log_debug() framework | Clifford Wolf | 2019-04-22 | 11 | -53/+183 | |
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| * | | | | | | | | | | | | | | | | | | | | Merge pull request #949 from YosysHQ/clifford/pmux2shimprove | Clifford Wolf | 2019-04-22 | 2 | -3/+24 | |
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| | * | | | | | | | | | | | | | | | | | | | | Updaye pmux2shiftx test | Clifford Wolf | 2019-04-22 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | | | | Add full_pmux feature to pmux2shiftx | Clifford Wolf | 2019-04-22 | 1 | -1/+22 | |
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| * | | | | | | | | | | | | | | | | | | | | Merge pull request #953 from YosysHQ/clifford/fix948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 | |
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| | * | | | | | | | | | | | | | | | | | | | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 | |
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| * | | | | | | | | | | | | | | | | | | | Merge pull request #950 from whitequark/attrmap_remove_wildcard | Clifford Wolf | 2019-04-22 | 1 | -1/+3 | |
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| | * | | | | | | | | | | | | | | | | | | attrmap: extend -remove to allow removing attributes with any value. | whitequark | 2019-04-22 | 1 | -1/+3 | |
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| * | | | | | | | | | | | | | | | | | | Set ENABLE_LIBYOSYS=0 by default | Clifford Wolf | 2019-04-22 | 1 | -1/+1 | |
| * | | | | | | | | | | | | | | | | | | Set ENABLE_PYOSYS=0 by default | Clifford Wolf | 2019-04-22 | 1 | -1/+1 | |
| * | | | | | | | | | | | | | | | | | | Merge pull request #905 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-22 | 15 | -10/+2472 | |
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| | * | | | | | | | | | | | | | | | | | Suppress error from the compiler run during libboost-python* detection | Benedikt Tutzer | 2019-04-07 | 1 | -4/+4 | |
| | * | | | | | | | | | | | | | | | | | Autodetect Python paths and boost python libraries for different distributions | Benedikt Tutzer | 2019-04-05 | 1 | -8/+24 | |
| | * | | | | | | | | | | | | | | | | | Used PyImport_ImportModule instead of PyImport_Import to avoid the explicit c... | Benedikt Tutzer | 2019-04-04 | 1 | -10/+2 | |
| | * | | | | | | | | | | | | | | | | | Removed link to experimental filesystem library | Benedikt Tutzer | 2019-04-04 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | Changed filesystem dependency to boost instead of experimental std library | Benedikt Tutzer | 2019-04-04 | 4 | -5/+11 | |
| | * | | | | | | | | | | | | | | | | | Removed compiler flags that are clang specific | Benedikt Tutzer | 2019-04-03 | 1 | -2/+2 | |
| | * | | | | | | | | | | | | | | | | | Even less options for the preprocessor | Benedikt Tutzer | 2019-04-03 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | Preprocessing does not need all the flags | Benedikt Tutzer | 2019-04-03 | 1 | -1/+1 | |
| | * | | | | | | | | | | | | | | | | | Global lists in rtlil.cc are now static objects | Benedikt Tutzer | 2019-04-03 | 1 | -10/+10 | |
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