| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | install *_nowide.lut files | Eddie Hung | 2019-06-29 | 2 | -0/+3 |
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| * | Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup | Eddie Hung | 2019-06-28 | 1 | -0/+1 |
| |\ | | | | | Make abc9 pass aware of optional ABCEXTERNAL override | ||||
| | * | Make abc9 pass aware of optional ABCEXTERNAL override | Gabriel L. Somlo | 2019-06-28 | 1 | -0/+1 |
| | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> | ||||
| * | | Replace log_assert() with meaningful log_error() | Eddie Hung | 2019-06-28 | 1 | -1/+5 |
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| * | | Remove peepopt call in synth_xilinx since already in synth -run coarse | Eddie Hung | 2019-06-28 | 1 | -5/+0 |
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| * | Add missing CHANGELOG entries | Eddie Hung | 2019-06-28 | 1 | -0/+3 |
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| * | Fix spacing | Eddie Hung | 2019-06-28 | 1 | -2/+2 |
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| * | Merge pull request #1098 from YosysHQ/xaig | Eddie Hung | 2019-06-28 | 45 | -247/+3642 |
| |\ | | | | | "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) | ||||
| | * | Add generic __builtin_bswap32 function | Eddie Hung | 2019-06-28 | 1 | -0/+15 |
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| | * | Also fix write_aiger for UB | Eddie Hung | 2019-06-28 | 1 | -26/+26 |
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| | * | Fix more potential for undefined behaviour due to container invalidation | Eddie Hung | 2019-06-28 | 1 | -6/+10 |
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| | * | Update synth_ice40 -device doc to be relevant for -abc9 only | Eddie Hung | 2019-06-28 | 1 | -2/+2 |
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| | * | Disable boxing of ECP5 dist RAM due to regression | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| | * | Add write address to abc_scc_break of ECP5 dist RAM | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| | * | Fix DO4 typo | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| | * | Reduce diff with upstream | Eddie Hung | 2019-06-27 | 1 | -4/+2 |
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| | * | Extraneous newline | Eddie Hung | 2019-06-27 | 1 | -1/+0 |
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| | * | Remove noise from ice40/cells_sim.v | Eddie Hung | 2019-06-27 | 1 | -5/+0 |
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| | * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 5 | -82/+84 |
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| | * | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 |
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| | | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 2 | -0/+19 |
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| | * | | | Do not use Module::remove() iterator version | Eddie Hung | 2019-06-27 | 1 | -5/+6 |
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| | * | | | Remove redundant doc | Eddie Hung | 2019-06-27 | 1 | -3/+0 |
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| | * | | | Remove &retime when abc9 -fast | Eddie Hung | 2019-06-27 | 1 | -1/+1 |
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| | * | | | Cleanup abc9.cc | Eddie Hung | 2019-06-27 | 1 | -15/+17 |
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| | * | | | Undo iterator based Module::remove() for cells, as containers will not | Eddie Hung | 2019-06-27 | 2 | -11/+2 |
| | |/ / | | | | | | | | | | invalidate | ||||
| | * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 4 | -9/+39 |
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| | * \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-27 | 0 | -0/+0 |
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| | * | | | | Add warning if synth_xilinx -abc9 with family != xc7 | Eddie Hung | 2019-06-27 | 1 | -0/+2 |
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| | * | | | | Remove unneeded include | Eddie Hung | 2019-06-27 | 1 | -3/+0 |
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| | * | | | | Merge origin/master | Eddie Hung | 2019-06-27 | 10 | -65/+480 |
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| | * | | | | Fix spacing | Eddie Hung | 2019-06-26 | 1 | -38/+38 |
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| | * | | | | Improve debugging message for comb loops | Eddie Hung | 2019-06-26 | 1 | -4/+6 |
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| | * | | | | Add WE to ECP5 dist RAM's abc_scc_break too | Eddie Hung | 2019-06-26 | 1 | -1/+1 |
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| | * | | | | Update comment on boxes | Eddie Hung | 2019-06-26 | 2 | -4/+6 |
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| | * | | | | Add "WE" to dist RAM's abc_scc_break | Eddie Hung | 2019-06-26 | 1 | -3/+3 |
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| | * | | | | Support more than one port in the abc_scc_break attr | Eddie Hung | 2019-06-26 | 1 | -38/+42 |
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| | * | | | | Add write_xaiger into CHANGELOG | Eddie Hung | 2019-06-26 | 1 | -0/+1 |
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| | * | | | | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 0 | -0/+0 |
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| | * | | | | | Remove unused var | Eddie Hung | 2019-06-26 | 1 | -1/+1 |
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| | * | | | | | Add _nowide variants of LUT libraries in -nowidelut flows | Eddie Hung | 2019-06-26 | 4 | -13/+44 |
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| | * | | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-26 | 1 | -2/+10 |
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| | | * \ \ \ \ | Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del | Eddie Hung | 2019-06-26 | 1 | -2/+10 |
| | | |\ \ \ \ \ | | | | | | | | | | | | | | | | | abc9: Add wire delays to synth_ice40 | ||||
| | | | * | | | | | abc9: Add wire delays to synth_ice40 | David Shah | 2019-06-26 | 1 | -2/+10 |
| | | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | | | | | | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 0 | -0/+0 |
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| | * \ \ \ \ \ \ | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 0 | -0/+0 |
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| | * \ \ \ \ \ \ \ | Merge branch 'koriakin/xc7nocarrymux' into xaig | Eddie Hung | 2019-06-26 | 2 | -9/+26 |
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| | * | | | | | | | | Missing muxpack.o in Makefile | Eddie Hung | 2019-06-25 | 1 | -0/+1 |
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| | * | | | | | | | | Realistic delays for RAM32X1D too | Eddie Hung | 2019-06-25 | 1 | -2/+2 |
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| | * | | | | | | | | Add RAM32X1D box info | Eddie Hung | 2019-06-25 | 2 | -4/+12 |
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index : iCE40/yosys | |
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