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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:16:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:16:15 -0700 |
| commit | b5f1bd0df1a467679a93d05604c6cc72696854ba (patch) | |
| tree | e0910ad5bd657c034d6c0f43121627e51323a611 | |
| parent | 4a2a93aa069db9397175a98a6836953ee71223d2 (diff) | |
| download | yosys-b5f1bd0df1a467679a93d05604c6cc72696854ba.tar.gz yosys-b5f1bd0df1a467679a93d05604c6cc72696854ba.tar.bz2 yosys-b5f1bd0df1a467679a93d05604c6cc72696854ba.zip | |
Add missing CHANGELOG entries
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -23,6 +23,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -nopartial" - Added "muxpack" pass - Added "pmux2shiftx -norange" + - Added "synth_xilinx -nocarry" + - Added "synth_xilinx -nowidelut" + - Added "synth_ecp5 -nowidelut" - Added "write_xaiger" backend - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) |