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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 09:46:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 09:46:36 -0700 |
| commit | 3f87575cb6cdace3de8dbe1b494e4d29a478878e (patch) | |
| tree | 964f93837e7f153d9f8eb8d917e382370c37d8dc | |
| parent | 0318860b93f7fa4eee148597811c77d67171e5d3 (diff) | |
| download | yosys-3f87575cb6cdace3de8dbe1b494e4d29a478878e.tar.gz yosys-3f87575cb6cdace3de8dbe1b494e4d29a478878e.tar.bz2 yosys-3f87575cb6cdace3de8dbe1b494e4d29a478878e.zip | |
Disable boxing of ECP5 dist RAM due to regression
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index acfb6960e..ca88d0a5b 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -104,7 +104,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) +//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |