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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 15:28:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 15:28:55 -0700 |
| commit | 312c03e4ca71f1560a9f47dcd2e9d3de1202179e (patch) | |
| tree | 0634a0fedc9ebfffaee8287fd0eda54a1671e495 | |
| parent | 137c91d9a98e05199b7acfe1d63139b79d278277 (diff) | |
| download | yosys-312c03e4ca71f1560a9f47dcd2e9d3de1202179e.tar.gz yosys-312c03e4ca71f1560a9f47dcd2e9d3de1202179e.tar.bz2 yosys-312c03e4ca71f1560a9f47dcd2e9d3de1202179e.zip | |
Remove redundant doc
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7dbd98055..c24f66e52 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -62,9 +62,6 @@ struct SynthXilinxPass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -nocarry\n"); - log(" disable inference of carry chains\n"); - log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); log("\n"); |