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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:10:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 11:10:36 -0700 |
| commit | 4a2a93aa069db9397175a98a6836953ee71223d2 (patch) | |
| tree | dd778b9c9a3c068ef020ce16b351a0499a5d308b | |
| parent | da5f83039527bf50af001671744f351988c3261a (diff) | |
| download | yosys-4a2a93aa069db9397175a98a6836953ee71223d2.tar.gz yosys-4a2a93aa069db9397175a98a6836953ee71223d2.tar.bz2 yosys-4a2a93aa069db9397175a98a6836953ee71223d2.zip | |
Fix spacing
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3721b82b7..f107f9947 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -673,8 +673,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } - for (auto cell : boxes) - module->remove(cell); + for (auto cell : boxes) + module->remove(cell); // Copy connections (and rename) from mapped_mod to module for (auto conn : mapped_mod->connections()) { |