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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 08:51:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-26 08:51:11 -0700 |
| commit | 4f0cb3449573acb189e877407d7b19a5d140c9e7 (patch) | |
| tree | 7aa49a38e06a3dba641096066c3fc7f06a224217 | |
| parent | 5db96b8aec7be2fb864d0f41ef21bb5168fa6b5c (diff) | |
| parent | 0dd850e6552a74430559ed63c3a9a67aa1c84512 (diff) | |
| download | yosys-4f0cb3449573acb189e877407d7b19a5d140c9e7.tar.gz yosys-4f0cb3449573acb189e877407d7b19a5d140c9e7.tar.bz2 yosys-4f0cb3449573acb189e877407d7b19a5d140c9e7.zip | |
Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del
abc9: Add wire delays to synth_ice40
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index d8e9786c5..a782f00b9 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -331,8 +331,16 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); } if (!noabc) { - if (abc == "abc9") - run(abc + stringf(" -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + if (abc == "abc9") { + int wire_delay; + if (device_opt == "lp") + wire_delay = 400; + else if (device_opt == "u") + wire_delay = 750; + else + wire_delay = 250; + run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); + } else run(abc + " -dress -lut 4", "(skip if -noabc)"); } |