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Revert #895
Eddie Hung
2019-04-16
1
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+0
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Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Eddie Hung
2019-04-15
2
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+3
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Revert "Recognise default entry in case even if all cases covered (fix for #9...
Eddie Hung
2019-04-15
2
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Merge pull request #936 from YosysHQ/README-fix-quotes
Eddie Hung
2019-04-15
1
-2
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+2
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README: fix some incorrect quoting.
whitequark
2019-04-15
1
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+2
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Merge pull request #928 from litghost/add_xc7_sim_models
Eddie Hung
2019-04-12
3
-41
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+60
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Keith Rothman
2019-04-12
3
-52
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+14
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Fix LUT6_2 definition.
Keith Rothman
2019-04-09
1
-3
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+3
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Add additional cells sim models for core 7-series primatives.
Keith Rothman
2019-04-09
1
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+57
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Merge pull request #933 from dh73/master
Clifford Wolf
2019-04-12
1
-3
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+9
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Fixing issues in CycloneV cell sim
Diego
2019-04-11
1
-3
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+9
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Merge pull request #932 from YosysHQ/eddie/fixdlatch
Clifford Wolf
2019-04-12
2
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+4
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Add default entry to testcase
Eddie Hung
2019-04-11
1
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+3
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Recognise default entry in case even if all cases covered (#931)
Eddie Hung
2019-04-11
1
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synth_* with -retime option now calls abc with -D 1 as well
Eddie Hung
2019-04-10
11
-15
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+15
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Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"
Eddie Hung
2019-04-10
1
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Revert ""&nf -D 0" fails => use "-D 1" instead"
Eddie Hung
2019-04-10
1
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Merge remote-tracking branch 'origin/master' into eddie/fix_retime
Eddie Hung
2019-04-10
2
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+5
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Fix a few typos
Eddie Hung
2019-04-08
1
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+3
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Merge pull request #919 from YosysHQ/multiport_transp
Clifford Wolf
2019-04-08
1
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+2
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memory_bram: Fix multiport make_transp
David Shah
2019-04-07
1
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+2
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Add retime test
Eddie Hung
2019-04-05
1
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+6
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Fix S0 -> S1
Eddie Hung
2019-04-05
1
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+1
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Move techamp t:$_DFF_?N? to before abc call
Eddie Hung
2019-04-05
1
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+2
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Retry
Eddie Hung
2019-04-05
1
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+1
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"&nf -D 0" fails => use "-D 1" instead
Eddie Hung
2019-04-05
1
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+1
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Resolve @daveshah1 comment, update synth_xilinx help
Eddie Hung
2019-04-05
2
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+9
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synth_xilinx to techmap FFs after abc call, otherwise -retime fails
Eddie Hung
2019-04-05
1
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+3
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abc -dff now implies "-D 0" otherwise retiming doesn't happen
Eddie Hung
2019-04-05
1
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+2
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Add "read_ilang -lib"
Clifford Wolf
2019-04-05
5
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+39
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Added missing argument checking to "mutate" command
Clifford Wolf
2019-04-04
1
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+32
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Merge pull request #913 from smunaut/fix_proc_mux
Eddie Hung
2019-04-03
1
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+1
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proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
Sylvain Munaut
2019-04-03
1
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+1
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Merge pull request #912 from YosysHQ/bram_addr_en
Clifford Wolf
2019-04-03
1
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+2
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memory_bram: Consider read enable for address expansion register
David Shah
2019-04-02
1
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+2
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Merge pull request #910 from ucb-bar/memupdates
Clifford Wolf
2019-04-03
1
-30
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+173
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Refine memory support to deal with general Verilog memory definitions.
Jim Lawson
2019-04-01
1
-30
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+173
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Merge pull request #895 from YosysHQ/pmux2shiftx
Eddie Hung
2019-04-02
1
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+28
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Create one $shiftx per bit in width
Eddie Hung
2019-03-25
1
-10
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+17
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Add a pmux-to-shiftx optimisation to proc_mux
Eddie Hung
2019-03-23
1
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+21
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Merge pull request #907 from YosysHQ/clifford/fix906
Clifford Wolf
2019-03-30
1
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+2
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Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Clifford Wolf
2019-03-29
1
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+2
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Merge pull request #901 from trcwm/libertyfixes
Clifford Wolf
2019-03-28
4
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+151
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Liberty file parser now accepts superfluous ;
Niels Moseley
2019-03-27
1
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+1
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Liberty file parser now accepts superfluous ;
Niels Moseley
2019-03-27
1
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+1
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Liberty file parser now accepts superfluous ;
Niels Moseley
2019-03-27
4
-9
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+151
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Merge pull request #903 from YosysHQ/bram_reset_transp
Clifford Wolf
2019-03-28
1
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+1
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memory_bram: Reset make_transp when growing read ports
David Shah
2019-03-27
1
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+1
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Add "read -verific" and "read -noverific"
Clifford Wolf
2019-03-27
1
-6
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+28
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Add "rename -output"
Clifford Wolf
2019-03-27
1
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+23
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