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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:39:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:39:05 -0700 |
| commit | 97587015748eb9f7e0d55a1121f604b8b462b45a (patch) | |
| tree | f832304b77a684897978348b6a151f49b450eaad | |
| parent | 23a6533e98df384afdeb38891404da17533c836b (diff) | |
| download | yosys-97587015748eb9f7e0d55a1121f604b8b462b45a.tar.gz yosys-97587015748eb9f7e0d55a1121f604b8b462b45a.tar.bz2 yosys-97587015748eb9f7e0d55a1121f604b8b462b45a.zip | |
Move techamp t:$_DFF_?N? to before abc call
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index abc164533..397c83ac6 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -111,10 +111,10 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); + log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); @@ -261,7 +261,6 @@ struct SynthXilinxPass : public Pass } else { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); @@ -269,6 +268,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); |