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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 16:28:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 16:28:14 -0700 |
| commit | d55902300772d90aee09555d412079e17fd4bde7 (patch) | |
| tree | b4b5293106809c904afed9a64c08b489ba5e27c6 | |
| parent | 97587015748eb9f7e0d55a1121f604b8b462b45a (diff) | |
| download | yosys-d55902300772d90aee09555d412079e17fd4bde7.tar.gz yosys-d55902300772d90aee09555d412079e17fd4bde7.tar.bz2 yosys-d55902300772d90aee09555d412079e17fd4bde7.zip | |
Fix S0 -> S1
| -rw-r--r-- | passes/techmap/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 4876f3009..e2a152348 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1728,7 +1728,7 @@ struct AbcPass : public Pass { signal_init[initsig[i]] = State::S0; break; case State::S1: - signal_init[initsig[i]] = State::S0; + signal_init[initsig[i]] = State::S1; break; default: break; |