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authorClifford Wolf <clifford@clifford.at>2019-03-30 00:09:42 +0100
committerGitHub <noreply@github.com>2019-03-30 00:09:42 +0100
commit22035c20ff071ec5c30990258850ecf97de5d5b3 (patch)
tree35cd5485c70c17e93426d54a104018bae90ed924
parent32bd0f22ec93202e67395901cdc64c20df7f0da7 (diff)
parent584d2030bf53c703febe8fda9cae73c72416c6cc (diff)
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Merge pull request #907 from YosysHQ/clifford/fix906
Build Verilog parser with -DYYMAXDEPTH=100000
-rw-r--r--frontends/verilog/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index dbaace585..0a1f97ac0 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -14,6 +14,8 @@ frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
$(Q) mkdir -p $(dir $@)
$(P) flex -o frontends/verilog/verilog_lexer.cc $<
+frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=100000
+
OBJS += frontends/verilog/verilog_parser.tab.o
OBJS += frontends/verilog/verilog_lexer.o
OBJS += frontends/verilog/preproc.o