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* Move CHANGELOG entry from yosys-0.8 to 0.9Eddie Hung2019-07-011-7/+1
* Merge branch 'master' into eddie/script_from_wireEddie Hung2019-07-014-5/+15
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| * Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOGEddie Hung2019-07-011-5/+11
| * Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-07-013-0/+4
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| | * install *_nowide.lut filesEddie Hung2019-06-292-0/+3
| | * Merge pull request #1149 from gsomlo/gls-1098-abcext-fixupEddie Hung2019-06-281-0/+1
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| | | * Make abc9 pass aware of optional ABCEXTERNAL overrideGabriel L. Somlo2019-06-281-0/+1
* | | | Merge branch 'master' into eddie/script_from_wireEddie Hung2019-06-281-1/+1
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| * | | autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-06-281-1/+1
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* | | Try command in another moduleEddie Hung2019-06-281-0/+3
* | | Add to CHANGELOGEddie Hung2019-06-281-0/+6
* | | Support ability for "script -select" to take commands from wiresEddie Hung2019-06-281-8/+39
* | | Add testEddie Hung2019-06-281-0/+17
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* | Replace log_assert() with meaningful log_error()Eddie Hung2019-06-281-1/+5
* | Remove peepopt call in synth_xilinx since already in synth -run coarseEddie Hung2019-06-281-5/+0
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* Add missing CHANGELOG entriesEddie Hung2019-06-281-0/+3
* Fix spacingEddie Hung2019-06-281-2/+2
* Merge pull request #1098 from YosysHQ/xaigEddie Hung2019-06-2845-247/+3642
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| * Add generic __builtin_bswap32 functionEddie Hung2019-06-281-0/+15
| * Also fix write_aiger for UBEddie Hung2019-06-281-26/+26
| * Fix more potential for undefined behaviour due to container invalidationEddie Hung2019-06-281-6/+10
| * Update synth_ice40 -device doc to be relevant for -abc9 onlyEddie Hung2019-06-281-2/+2
| * Disable boxing of ECP5 dist RAM due to regressionEddie Hung2019-06-281-1/+1
| * Add write address to abc_scc_break of ECP5 dist RAMEddie Hung2019-06-281-1/+1
| * Fix DO4 typoEddie Hung2019-06-281-1/+1
| * Reduce diff with upstreamEddie Hung2019-06-271-4/+2
| * Extraneous newlineEddie Hung2019-06-271-1/+0
| * Remove noise from ice40/cells_sim.vEddie Hung2019-06-271-5/+0
| * Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-275-82/+84
| * Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-272-0/+19
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| | * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-272-0/+19
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| * | | Do not use Module::remove() iterator versionEddie Hung2019-06-271-5/+6
| * | | Remove redundant docEddie Hung2019-06-271-3/+0
| * | | Remove &retime when abc9 -fastEddie Hung2019-06-271-1/+1
| * | | Cleanup abc9.ccEddie Hung2019-06-271-15/+17
| * | | Undo iterator based Module::remove() for cells, as containers will notEddie Hung2019-06-272-11/+2
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| * | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-274-9/+39
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| * \ \ Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-270-0/+0
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| * | | | Add warning if synth_xilinx -abc9 with family != xc7Eddie Hung2019-06-271-0/+2
| * | | | Remove unneeded includeEddie Hung2019-06-271-3/+0
| * | | | Merge origin/masterEddie Hung2019-06-2710-65/+480
| * | | | Fix spacingEddie Hung2019-06-261-38/+38
| * | | | Improve debugging message for comb loopsEddie Hung2019-06-261-4/+6
| * | | | Add WE to ECP5 dist RAM's abc_scc_break tooEddie Hung2019-06-261-1/+1
| * | | | Update comment on boxesEddie Hung2019-06-262-4/+6
| * | | | Add "WE" to dist RAM's abc_scc_breakEddie Hung2019-06-261-3/+3
| * | | | Support more than one port in the abc_scc_break attrEddie Hung2019-06-261-38/+42
| * | | | Add write_xaiger into CHANGELOGEddie Hung2019-06-261-0/+1
| * | | | Merge branch 'koriakin/xc7nocarrymux' into xaigEddie Hung2019-06-260-0/+0
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| * | | | | Remove unused varEddie Hung2019-06-261-1/+1
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