| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | | | | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync | Eddie Hung | 2019-10-08 | 3 | -13/+19 | |
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| | * | | | | | | | Add -async2sync to help text as per @daveshah1 | Eddie Hung | 2019-10-04 | 1 | -1/+4 | |
| | * | | | | | | | Restore part of doc | Eddie Hung | 2019-10-03 | 1 | -1/+2 | |
| | * | | | | | | | Disable equiv check for ice40 latches | Eddie Hung | 2019-10-03 | 1 | -6/+3 | |
| | * | | | | | | | Add new -async2sync option | Eddie Hung | 2019-10-03 | 1 | -1/+11 | |
| | * | | | | | | | Use equiv_opt -async2sync for xilinx | Eddie Hung | 2019-10-03 | 1 | -3/+1 | |
| | * | | | | | | | Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys" | Eddie Hung | 2019-10-03 | 1 | -2/+0 | |
| | * | | | | | | | Revert "Update doc for equiv_opt" | Eddie Hung | 2019-10-03 | 1 | -3/+2 | |
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| * | | | | | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 34 | -309/+316 | |
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| | * \ \ \ \ \ \ | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 8 | -185/+33 | |
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| | * | | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 34 | -305/+313 | |
| * | | | | | | | | | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments | Eddie Hung | 2019-10-08 | 5 | -72/+364 | |
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| | * | | | | | | | | | Missed this | Eddie Hung | 2019-10-05 | 1 | -3/+4 | |
| | * | | | | | | | | | Add comment on why we have to match for clock-enable/reset muxes | Eddie Hung | 2019-10-05 | 3 | -3/+11 | |
| | * | | | | | | | | | Add note on pattern detector | Eddie Hung | 2019-10-05 | 1 | -3/+7 | |
| | * | | | | | | | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 | |
| | * | | | | | | | | | Add comments for xilinx_dsp_cascade | Eddie Hung | 2019-10-04 | 1 | -12/+100 | |
| | * | | | | | | | | | Improve comments for xilinx_dsp_CREG | Eddie Hung | 2019-10-04 | 1 | -6/+7 | |
| | * | | | | | | | | | Fix comment | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | * | | | | | | | | | Restore optimisation for sigM.empty() | Eddie Hung | 2019-10-04 | 1 | -1/+4 | |
| | * | | | | | | | | | Retry on fixing TODOs | Eddie Hung | 2019-10-04 | 2 | -13/+1 | |
| | * | | | | | | | | | Revert "Fix TODOs" | Eddie Hung | 2019-10-04 | 2 | -0/+20 | |
| | * | | | | | | | | | More comments, cleanup | Eddie Hung | 2019-10-04 | 2 | -41/+108 | |
| | * | | | | | | | | | Fix TODOs | Eddie Hung | 2019-10-04 | 2 | -20/+0 | |
| | * | | | | | | | | | Consistency | Eddie Hung | 2019-10-04 | 1 | -3/+3 | |
| | * | | | | | | | | | Add comments for xilinx_dsp | Eddie Hung | 2019-10-04 | 3 | -6/+134 | |
| * | | | | | | | | | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry | Clifford Wolf | 2019-10-06 | 2 | -0/+26 | |
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| | * | | | | | | | | | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf | Eddie Hung | 2019-10-05 | 2 | -0/+26 | |
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| * | | | | | | | | | | Update README.md | Clifford Wolf | 2019-10-05 | 1 | -1/+1 | |
| * | | | | | | | | | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fix | Miodrag Milanović | 2019-10-05 | 2 | -2/+7 | |
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| | * | | | | | | | | | Fixes for MSVC build | Miodrag Milanovic | 2019-10-04 | 2 | -2/+7 | |
| * | | | | | | | | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| * | | | | | | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 2 | -5/+19 | |
| * | | | | | | | | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 | |
| * | | | | | | | | | Fix xilinx_dsp for unsigned extensions | Eddie Hung | 2019-10-04 | 1 | -1/+3 | |
| * | | | | | | | | | Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again | Eddie Hung | 2019-10-04 | 1 | -0/+6 | |
| * | | | | | | | | | Add Const::{begin,end,empty}() | Eddie Hung | 2019-10-04 | 1 | -0/+3 | |
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| * | | | | | | | | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 | |
| * | | | | | | | | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| * | | | | | | | | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 | |
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| | | | | * | | | hierarchy - proc reorder | Miodrag Milanovic | 2019-10-18 | 9 | -14/+18 | |
| | | | | * | | | Check latches type one by one | Miodrag Milanovic | 2019-10-04 | 2 | -40/+25 | |
| | | | | * | | | Removed top module where not needed | Miodrag Milanovic | 2019-10-04 | 4 | -37/+4 | |
| | | | | * | | | Test muxes synth one by one | Miodrag Milanovic | 2019-10-04 | 2 | -38/+39 | |
| | | | | * | | | Cleaned verilog code from not used defines | Miodrag Milanovic | 2019-10-04 | 1 | -6/+0 | |
| | | | | * | | | Check for MULT18X18D, since that is working now | Miodrag Milanovic | 2019-10-04 | 2 | -14/+11 | |
| | | | | * | | | Check flops one by one | Miodrag Milanovic | 2019-10-04 | 4 | -71/+50 | |
| | | | | * | | | Removed alu and div_mod tests as agreed | Miodrag Milanovic | 2019-10-04 | 4 | -57/+0 | |
| | | | | * | | | equiv_opt with -assert | Eddie Hung | 2019-09-30 | 1 | -3/+1 | |
| | | | | * | | | Update resource count for alu.ys | Eddie Hung | 2019-09-30 | 1 | -3/+3 | |
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