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| * | | | | | | | techmap: simplify.whitequark2020-06-021-7/+1
| * | | | | | | | techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-023-16/+1
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* | | | | | | | Merge pull request #2102 from YosysHQ/tests_fixclairexen2020-06-021-1/+2
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| * | | | | | | | allow range for mux testMiodrag Milanovic2020-06-011-1/+2
* | | | | | | | | Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetricclairexen2020-06-021-6/+1
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| * | | | | | | | Support asymmetric memories for verific frontendMiodrag Milanovic2020-06-011-6/+1
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* | | | | | | | Merge pull request #1862 from boqwxp/cleanup_techmapclairexen2020-05-315-153/+169
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| * | | | | | | | kernel: Try an order-independent approach to hashing `dict`.Alberto Gonzalez2020-05-191-5/+3
| * | | | | | | | kernel: Ensure `dict` always hashes to the same value given the same contents.Alberto Gonzalez2020-05-141-3/+6
| * | | | | | | | kernel: Re-implement `dict` hash code as a `dict` member function instead of ...Alberto Gonzalez2020-05-141-20/+14
| * | | | | | | | techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| * | | | | | | | techmap: Replace pseudo-private member usage with the range accessor function...Alberto Gonzalez2020-05-141-3/+3
| * | | | | | | | techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
| * | | | | | | | Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| * | | | | | | | techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-143-12/+14
| * | | | | | | | Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| * | | | | | | | Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
| * | | | | | | | Build constant bits directly rather than constructing an object and copying i...Alberto Gonzalez2020-05-141-2/+5
| * | | | | | | | Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
| * | | | | | | | Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
| * | | | | | | | Clean up pseudo-private member usage and ensure range iteration uses referenc...Alberto Gonzalez2020-05-141-17/+17
| * | | | | | | | Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
| * | | | | | | | Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
| * | | | | | | | Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `c...Alberto Gonzalez2020-05-141-3/+3
| * | | | | | | | Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and `outb...Alberto Gonzalez2020-05-141-3/+3
| * | | | | | | | Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
| * | | | | | | | Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
| * | | | | | | | Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
| * | | | | | | | Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
| * | | | | | | | Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::...Alberto Gonzalez2020-05-143-10/+25
| * | | | | | | | Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-143-5/+5
| * | | | | | | | Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
| * | | | | | | | Replace `std::string` and `RTLIL::IdString` with `IdString` in `passes/techma...Alberto Gonzalez2020-05-141-21/+21
| * | | | | | | | Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| * | | | | | | | Clean up pseudo-private member usage, superfluous `std::vector` instantiation...Alberto Gonzalez2020-05-141-76/+70
* | | | | | | | | Merge pull request #2081 from YosysHQ/eddie/blackbox_astEddie Hung2020-05-301-25/+1
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| * | | | | | | | | blackbox: re-use existing Module::makeblackbox() methodEddie Hung2020-05-251-25/+1
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* | | | | | | | | Merge pull request #2018 from boqwxp/qbfsat-timeoutclairexen2020-05-303-18/+84
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| * | | | | | | | smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.Alberto Gonzalez2020-05-291-4/+0
| * | | | | | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, a...Alberto Gonzalez2020-05-253-18/+88
* | | | | | | | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-293-2/+11
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| * | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-053-2/+11
* | | | | | | | | | Merge pull request #1885 from Xiretza/mod-rem-cellsclairexen2020-05-2926-40/+540
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| * | | | | | | | | | Document division and modulo cellsXiretza2020-05-281-0/+23
| * | | | | | | | | | Update CHANGELOGXiretza2020-05-281-0/+1
| * | | | | | | | | | Add comments for mod/div semantics to rtlil.hXiretza2020-05-281-0/+4
| * | | | | | | | | | Expand tests/simple/constmuldivmod.vXiretza2020-05-281-1/+41
| * | | | | | | | | | Add flooring division operatorXiretza2020-05-2819-24/+213
| * | | | | | | | | | Add flooring modulo operatorXiretza2020-05-2823-37/+280
* | | | | | | | | | | Merge pull request #2092 from whitequark/rtlil-no-space-controlclairexen2020-05-292-6/+11
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