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| author | clairexen <claire@symbioticeda.com> | 2020-05-29 16:52:11 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-29 16:52:11 +0200 |
| commit | 0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3 (patch) | |
| tree | 2af754e54f6bd38da670fadd9fac7aaa6a1b48d3 | |
| parent | 94c10353897c6b2b3f960bdd6647a5da9c1d9f2c (diff) | |
| parent | 66d0ed2bcc7195aab5b107b2536e6818fe5b244c (diff) | |
| download | yosys-0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3.tar.gz yosys-0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3.tar.bz2 yosys-0a14e1e837ad0aeae6944a9eafe1a14b79c12cb3.zip | |
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
ast/simplify: don't bitblast async ROMs declared as `logic`
| -rw-r--r-- | frontends/ast/simplify.cc | 4 | ||||
| -rw-r--r-- | tests/svtypes/logic_rom.sv | 6 | ||||
| -rw-r--r-- | tests/svtypes/logic_rom.ys | 3 |
3 files changed, 11 insertions, 2 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3314819fb..3d690c1f5 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3540,8 +3540,8 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg } } - // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' - if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg)) + // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic' + if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic))) mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED; if (type == AST_MODULE && get_bool_attribute(ID::mem2reg)) diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv new file mode 100644 index 000000000..45fe0a4ca --- /dev/null +++ b/tests/svtypes/logic_rom.sv @@ -0,0 +1,6 @@ +module top(input [3:0] addr, output [7:0] data); + logic [7:0] mem[0:15]; + assign data = mem[addr]; + integer i; + initial for(i = 0; i < 16; i = i + 1) mem[i] = i; +endmodule diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys new file mode 100644 index 000000000..7b079c136 --- /dev/null +++ b/tests/svtypes/logic_rom.ys @@ -0,0 +1,3 @@ +read_verilog -sv logic_rom.sv +prep -top top +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i |