index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
Commit message (
Expand
)
Author
Age
Files
Lines
...
*
|
|
|
Fix gcc invalidation behaviour for write_aiger
Eddie Hung
2019-06-20
1
-1
/
+2
*
|
|
|
Fix gcc error, due to dict invalidation during recursion
Eddie Hung
2019-06-20
2
-4
/
+5
*
|
|
|
Fix gcc warning of potentially uninitialised
Eddie Hung
2019-06-20
1
-2
/
+2
*
|
|
|
write_xaiger to flatten 1'bx/1'bz to 1'b0 again
Eddie Hung
2019-06-20
1
-2
/
+4
*
|
|
|
Fix simple_abc9/generate test with 1'bx at MSB
Eddie Hung
2019-06-20
1
-1
/
+1
*
|
|
|
Fix different abc9 test
Eddie Hung
2019-06-20
1
-2
/
+3
*
|
|
|
Fix broken abc9.v test due to inout being 1'bx
Eddie Hung
2019-06-20
2
-5
/
+21
*
|
|
|
Run simple_abc9 tests
Eddie Hung
2019-06-20
1
-0
/
+1
*
|
|
|
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-20
31
-50
/
+250
|
\
|
|
|
|
*
|
|
Fix typo, fixes #1095
Clifford Wolf
2019-06-20
1
-1
/
+1
|
*
|
|
Improve shregmap help message, fixes #1113
Clifford Wolf
2019-06-20
1
-0
/
+2
|
*
|
|
Update some .gitignore files
Clifford Wolf
2019-06-20
2
-3
/
+3
|
*
|
|
Fix typo
Clifford Wolf
2019-06-20
1
-2
/
+2
|
*
|
|
Merge branch 'towoe-unpacked_arrays'
Clifford Wolf
2019-06-20
2
-1
/
+23
|
|
\
\
\
|
|
|
/
/
|
|
/
|
|
|
|
*
|
Add proper test for SV-style arrays
Clifford Wolf
2019-06-20
3
-6
/
+16
|
|
*
|
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...
Clifford Wolf
2019-06-20
3
-1
/
+13
|
|
/
|
|
|
|
*
|
Unpacked array declaration using size
Tobias Wölfel
2019-06-19
3
-1
/
+13
|
*
|
|
Merge pull request #1111 from acw1251/help_summary_fixes
Eddie Hung
2019-06-19
4
-6
/
+6
|
|
\
\
\
|
|
*
|
|
Fixed small typo in ice40_unlut help summary
acw1251
2019-06-19
1
-1
/
+1
|
|
*
|
|
Fixed the help summary line for a few commands
acw1251
2019-06-19
4
-6
/
+6
|
|
/
/
/
|
*
|
|
Fix bug in #1078, add entry to CHANGELOG
Eddie Hung
2019-06-19
2
-3
/
+4
|
*
|
|
Merge pull request #1109 from YosysHQ/clifford/fix1106
Clifford Wolf
2019-06-19
6
-9
/
+48
|
|
\
\
\
|
|
*
|
|
Add "read_verilog -pwires" feature, closes #1106
Clifford Wolf
2019-06-19
6
-9
/
+48
|
|
/
/
/
|
*
|
|
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Clifford Wolf
2019-06-19
5
-16
/
+92
|
|
\
\
\
|
|
*
|
|
Add defvalue test, minor autotest fixes for .sv files
Clifford Wolf
2019-06-19
2
-14
/
+37
|
|
*
|
|
Use input default values in hierarchy pass
Clifford Wolf
2019-06-19
1
-0
/
+38
|
|
*
|
|
Add defaultvalue attribute
Clifford Wolf
2019-06-19
2
-0
/
+15
|
|
*
|
|
Fix handling of "logic" variables with initial value
Clifford Wolf
2019-06-19
1
-2
/
+2
|
*
|
|
|
Make tests/aiger less chatty
Clifford Wolf
2019-06-19
1
-4
/
+6
|
|
/
/
/
|
*
|
|
Merge pull request #1100 from bwidawsk/home
Clifford Wolf
2019-06-19
5
-0
/
+8
|
|
\
\
\
|
|
*
|
|
Support filename rewrite in backends
Ben Widawsky
2019-06-18
4
-0
/
+4
|
|
*
|
|
Support ~ for home directory
Ben Widawsky
2019-06-18
1
-0
/
+4
|
*
|
|
|
Merge pull request #1104 from whitequark/case-semantics
Clifford Wolf
2019-06-19
2
-1
/
+40
|
|
\
\
\
\
|
|
|
/
/
/
|
|
/
|
|
|
|
|
*
|
|
Explain exact semantics of switch and case rules in the manual.
whitequark
2019-06-19
1
-0
/
+12
|
|
*
|
|
In RTLIL::Module::check(), check process invariants.
whitequark
2019-06-19
1
-1
/
+28
|
|
/
/
/
|
*
|
|
Merge pull request #1086 from udif/pr_elab_sys_tasks2
Clifford Wolf
2019-06-18
2
-3
/
+13
|
|
\
\
\
|
|
|
/
/
|
|
/
|
|
|
|
*
|
Fixed brojen $error()/$info/$warning() on non-generate blocks
Udi Finkelstein
2019-06-11
2
-3
/
+13
|
*
|
|
Add timescale and generated-by header to yosys-smtbmc MkVcd
Clifford Wolf
2019-06-16
1
-0
/
+2
*
|
|
|
Fix issue with part of PI being 1'bx
Eddie Hung
2019-06-20
2
-4
/
+11
*
|
|
|
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
Eddie Hung
2019-06-20
1
-0
/
+1
*
|
|
|
Handle COs driven by 1'bx
Eddie Hung
2019-06-20
1
-3
/
+9
*
|
|
|
Do not call "setundef -zero" in abc9
Eddie Hung
2019-06-20
1
-5
/
+2
*
|
|
|
write_xaiger to skip POs driven by 1'bx
Eddie Hung
2019-06-20
1
-3
/
+7
*
|
|
|
Really permute Xilinx LUT mappings as default LUT6.I5:A6
Eddie Hung
2019-06-18
1
-16
/
+16
*
|
|
|
Revert "Fix (do not) permute LUT inputs, but permute mux selects"
Eddie Hung
2019-06-18
1
-33
/
+31
*
|
|
|
Clean up
Eddie Hung
2019-06-18
1
-6
/
+4
*
|
|
|
Fix (do not) permute LUT inputs, but permute mux selects
Eddie Hung
2019-06-18
1
-31
/
+33
*
|
|
|
Fix copy-pasta issue
Eddie Hung
2019-06-17
1
-9
/
+8
*
|
|
|
Permute INIT for +/xilinx/lut_map.v
Eddie Hung
2019-06-17
1
-32
/
+58
*
|
|
|
Simplify comment
Eddie Hung
2019-06-17
1
-1
/
+1
[prev]
[next]
