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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:29:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:38:16 -0700 |
| commit | 014606affe3f1753ac16d2afd684967d72d83746 (patch) | |
| tree | 81d40c59523c214e1d63c50b41adbc8f59f6c49e | |
| parent | f11c9a419b99563b462356add5446d9fc2dbe2eb (diff) | |
| download | yosys-014606affe3f1753ac16d2afd684967d72d83746.tar.gz yosys-014606affe3f1753ac16d2afd684967d72d83746.tar.bz2 yosys-014606affe3f1753ac16d2afd684967d72d83746.zip | |
Fix issue with part of PI being 1'bx
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 10 | ||||
| -rw-r--r-- | tests/simple_abc9/abc9.v | 5 |
2 files changed, 11 insertions, 4 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 3b53b0086..ea3315267 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -947,11 +947,13 @@ void AigerReader::post_process() if (other_wire) { other_wire->port_input = false; other_wire->port_output = false; - if (wire->port_input) - module->connect(other_wire, SigSpec(wire, i)); - else - module->connect(SigSpec(wire, i), other_wire); } + if (wire->port_input && other_wire) + module->connect(other_wire, SigSpec(wire, i)); + else + // Since we skip POs that are connected to Sx, + // re-connect them here + module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx)); } } diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 0b83c34a3..64b625efe 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -262,3 +262,8 @@ endmodule module abc9_test025(input [3:0] i, output [3:0] o); abc9_test024_sub a(i[2:1], o[2:1]); endmodule + +module abc9_test026(output [3:0] o, p); +assign o = { 1'b1, 1'bx }; +assign p = { 1'b1, 1'bx, 1'b0 }; +endmodule |